Freescale Semiconductor
Advance Information
Document Number: MC34652
Rev. 8.0, 2/2007
2.0 A Negative Voltage Hot
Swap Controller with Enhanced
Programmability
The 34652 is a highly integrated - 48 V hot swap controller with an
internal Power MOSFET. It provides the means to safely install and
remove boards from live - 48 V backplanes without having to power
down the entire system. It regulates the inrush current, from the
supply to the load’s filter capacitor, to a user-programmable limit,
allowing the system to safely stabilize. A disable function allows the
user to disable the 34652 manually or through a microprocessor and
safely disconnect the load from the main power line.
The 34652 has active high and active low power good output
signals that can be used to directly enable a power module load.
Programmable under- and overvoltage detection circuitry monitors
the input voltage to check that it is within its operating range.
A programmable start-up delay timer ensures that it is safe to turn on
the Power MOSFET and charge the load capacitor.
A two-level current limit approach to controlling the inrush current
and switching on the load limits the peak power dissipation in the
Power MOSFET. Both current limits are user programmable.
Features
• Integrated Power MOSFET and Control IC in a Small Outline
Package
• Input Voltage Operation Range from -15 V to - 80 V
• Programmable Overcurrent Limit with Auto Retry
• Programmable Charging Current Limit Independent of Load
Capacitor
• Programmable Start-Up and Retry Delay Timer
• Programmable Overvoltage and Undervoltage Detection
• Active High and Low Power Good Output Signals
• Thermal Shutdown
• Pb-Free Packaging Designated by Suffix Code EF
34652
HOT SWAP
SCALE 2:1
EF SUFFIX (PB-Free)
98ASB42566B
16-PIN SOICN
ORDERING INFORMATION
Device
MC34652EF/ R2
- 40°C to 85°C
MCZ34652EF/ R2
16 SOICN
Temperature
Range (T
A
)
Package
34652
DISABLE
PG
GND
System
Power
Supply
(Backplane)
-48 V
VPWR
PG
UV
OV
VIN
ICHG
Optional
External
Components
ILIM
TIMER
Optional
External
Components
VOUT
Load
Application
Dependent
Figure 1. 34652 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
DISABLE
Referenced VPWR
Logic
Fixed
Oscillator
Adjustable Oscillator
and
Startup Delay Timer
Timer
and
External
Resistors
Detection
TIMER
VPWR
PG
-
1.3 V
+
UVLO
UV
-
1.3 V
+
Logic
UV
PG
OV
+
1.3 V
-
OV
VIN
Thermal
Shutdown
ILIM
3.1 V
External
Resistors
Detection
Programmable
Current Limit
Gate Control
Driver
Sensor MOSFET
8.0 µA
ICHG
VIN
Power MOSFET
VOUT
Figure 2. 34652 Simplified Internal Block Diagram
34652
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VIN
PG
PG
VOUT
VOUT
TIMER
NC
VIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN
ICHG
ILIM
DISABLE
VPWR
UV
OV
VIN
Figure 3. 16-SOICN Pin Connections
Table 1. 16-SOICN Pin Definitions
A functional description of each pin can be found in the
FUNCTIONAL PIN DESCRIPTION
section beginning on
page 10.
Pin
1, 8, 9, 16
2
3
4, 5
6
7
10
11
12
13
Pin Name
VIN
PG
PG
VOUT
TIMER
NC
OV
UV
VPWR
DISABLE
Formal Name
Negative Supply
Input Voltage
Power Good Output
(Active High)
Power Good Output
(Active Low)
Output Voltage
Start-Up and Retry
Delay Timer
No Connect
Overvoltage Control
Undervoltage Control
Positive Supply
Input Voltage
Disable Input Control
Definition
This is the most negative power supply input. All pins except DISABLE are referenced
to this input.
This is an active high power good output signal. This pin is referenced to VIN.
This is an active low power good output signal. This pin is referenced to VIN.
This pin is the drain of the internal Power MOSFET and supplies a current limited voltage
to the load.
This input is used to control the time base used to generate the timing sequences at
start-up and the retry delay when the device experiences any fault.
Not connected.
This pin is used to set the upper limit of the input voltage operation range.
This pin is used to set the lower limit of the input voltage operation range.
This is the most-positive power supply input. The load connects between this pin and the
VOUT pin.
This pin is used to easily disconnect or connect the load from the main power line by
disabling or enabling the 34652. It can also be used to reset the fault conditions that
cause a “Power No Good” signal. This pin is referenced to VPWR.
This pin is used to set the overcurrent limit during normal operation.
This pin is used to set the load’s input capacitor charging current limit, hence limiting the
inrush current to a known constant value.
14
15
ILIM
ICHG
Current Limit Control
Charging Current
Limit Control
34652
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
ELECTRICAL RATINGS
Power Supply Voltage
Power MOSFET Energy Capability
Continuous Output Current
(2)
Maximum Voltage
DISABLE Pin
UV Pin
OV, ILIM, ICHG, and TIMER Pins
PG Pin (V
PG
- V
IN
)
PG
Pin (V
PG
- V
IN
)
Symbol
Value
Unit
V
PWR
E
MOSFET
I
O (CONT
)
—
—
—
—
—
—
—
V
ESD3
V
ESD4
85
Varies
(1)
2.0
V
mJ
A
V
V
IN
- 0.3 to V
PWR
+ 5.5
7.0
5.0
85
85
- 0.3
Internally Limited
± 2000
± 200
V
A
V
All Pins Minimum Voltage
PG,
PG
Maximum Current
ESD Voltage, All Pins
(3)
Human Body Model
Machine Model
THERMAL RATINGS
Storage Temperature
Operating Temperature
Ambient
(4)
Junction
T
STG
T
A
T
J
- 65 to 150
°C
°C
- 40 to 85
- 40 to 160
Notes
1. Refer to the section titled
Power MOSFET Energy Capability on page 23
for a detailed explanation on this parameter.
2. Continuous output current capability so long as T
J
is
≤
160
°
C.
3.
4.
ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100pF, R
ZAP
= 1500
Ω),
ESD2 testing is performed in
accordance with the Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
Ω).
The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking.
34652
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
ELECTRICAL RATINGS
Peak Package Reflow Temperature During Reflow
(5), (6)
Thermal Resistance
(7)
,
(8)
(9)
Symbol
Value
Unit
T
PPRT
Note 6
°C
°C/W
Junction-to-Ambient, Single-Layer Board
R
θ
JA
R
θ
JMA
103
65
Junction-to-Ambient, Four-Layer Board
(10)
Notes
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
7. Refer to the section titled
Thermal Shutdown on page 16
for more thermal resistance values under various conditions.
8. The VOUT and VIN pins comprise the main heat conduction paths.
9. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
10. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are no thermal vias connecting the package to the two planes in the
board.
34652
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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