DPDD64MX4TSAY5-DP-XX1030 datasheet, PDF

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DPDD64MX4TSAY5-DP-XX1030: DescriptionDDR DRAM Module, 64MX4, CMOS, LEADED STACK, TSOP-66; Categorystorage storage; File Size155KB，2 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPDD64MX4TSAY5-DP-XX1030 Overview

DDR DRAM Module, 64MX4, CMOS, LEADED STACK, TSOP-66

DPDD64MX4TSAY5-DP-XX1030 Parametric

Parameter Name	Attribute value
Maker	B&B Electronics Manufacturing Company
Parts packaging code	DMA
package instruction	,
Contacts	66
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-G66
memory density	268435456 bit
Memory IC Type	DDR DRAM MODULE
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	66
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
organize	64MX4
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
self refresh	YES
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal location	DUAL
Base Number Matches	1

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ADVANCE D COM P ON E NTS PACKAG I NG

256 Megabit CMOS DDR SDRAM

DPDD64MX4TSAY5

DESCRIPTION:

The Memory Stack™ series is a family of interchangeable memory moduels. The 256 Megabit Double Data Rate Synchronous

DRAM module is a member of this family which utilizes the space saving LP-Stack™ TSOP stacking technology. The devices are

constructed with two 32 Meg x 4 DDR SDRAMs.

This 128 Megabit based LP-Stack™ module,

DPDD64MX4TSAY5, has been designed to fit in the same

footprint as the 32 Meg x 4 DDR SDRAM TSOP monolithic.

This allows system upgrade without electrical or mechanical

redesign, providing an immediate and low cost memory

solution.

FEATURES:

• Configuration Available:

64 Meg x 4 (2 Banks of 8 Meg x 4 bits x 4 banks)

• Clock Frequency: 100, 125, 133, 143, 167 MHz (max.)

• 2.5 Volt DQ Supply

• JEDEC Standard SSTL_2 Interface for all Inputs/Outputs

• Four Bank Operation

• Programmable Burst Type: Burst Length and Read Latency

• Refresh: 4096 Cycles/64ms

• Refresh Types: Auto and Self

• IPC-A-610 Manufacturing Standards

• JEDEC Approved Footprint and Pinout

• Package: 66-Pin Leaded TSOP Stack

PIN-OUT DIAGRAM

VDD

N.C.

VDDQ

N.C.

DQ0

VSSQ

N.C.

VDDQ

N.C.

DQ1

VSSQ

N.C.

VDDQ

N.C.

VDD

*NU/QFC

N.C.

CAS

RAS

CS0

CS1

BA0

BA1

A10/AP

VDD

VSS

N.C.

VSSQ

N.C.

DQ3

VDDQ

N.C.

VSSQ

N.C.

DQ2

VDDQ

N.C.

VSSQ

DQS

N.C.

VREF

VSS

CKE0

CKE1

N.C.

A11

VSS

(TOP VIEW)

PIN NAMES

A0-A11

BA0,BA1

A10/AP

DQ0-DQ3

CAS

CS0, CS1

RAS

CK, CK

CKE0, CKE1

DQS

QFC

Vss

DDQ

Vss

REF

N.C.

30A234-00

REV. D 3/02

Row Address:

Column Address:

Bank Select Address

Auto Precharge

Data In/Data Out

A0-A11

A0-A9, A11

* This pin is a No Connect for some manufacturers.

Column Address Strobe

Chip Selects

Row Address Strobe

Data Write Enable

Differential Clock Inputs

Clock Enables

Data Strobe

Data Mask

DQ FET Switch Control

Power Supply (+2.5V)

Ground

DQ Power Supply (+2.5V)

DQ Ground

Reference Voltage for inputs

No Connect

Not Used, Electrical Connect is Present

FUNCTIONAL BLOCK DIAGRAM

CS0

CKE0

RAS

CAS

*QFC

VREF

DQS

A0-A11

BA0-BA1

128 Mb DDR SDRAM

(8 Meg x 4 Bits x 4 Banks)

CS1

CKE1

DQ0-DQ3

This document contains information on a product that is currently released to production at DPAC Technologies.

DPAC reserves the right to change products or specifications herein without prior notice.

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