CALIFORNIA MICRO DEVICES
PRN299
Applications
POSITIVE / PSEUDO ECL (PECL) CLOCK TERMINATION NETWORK
Features
Stable resistor network
Reduces power dissipation on the clock lines
Ideal for high-speed clock termination
Reduces board space by 70% vs. 1206 discretes
and component count by more than 50%
PECL clock termination
Application Note
High speed microprocessors line Intels Pentium/P6®, Apple PowerPC®, SPARC® and other CISC and RISC based systems need
well-controlled and precise clock signals to maintain a synchronous systems. The fast edge rated clock signals will exhibit
transmission line effects on the clock lines resulting in undershoots and overshoots. The integrated PECL termination is
designed to suppress the undershoots and overshoots on the clock lines. The PECL RC terminator dissipates very low power
compared to the resistor termination network.
Why thin.film R networks?
The PECL termination is an integrated R network fabricated on a silicon substrate using
advanced thin film technology. This will have a fixed time constant and will not create additional skew on the clock lines. It
has a low parasitic inductance compared to discrete and conventional thick film R terminators and provide effective termination
at high frequencies.
STANDARD VALUES
R
1
(Ω
)
±
1%
Ω
50
R
2
(Ω
)
±
1%
Ω
50
R
3
(Ω
)
±
1%
Ω
46.4
SCHEMATIC DIAGRAM
Pins
3
ST
ANDAR
D PART ORDE RING INFORMATION
Package
Ordering Part Number
Style
Part Marking
SOT-23
P R N 299
When placing an order please specify desired shipping: Tubes or Tape & Reel.
© 2000 California Micro Devices Corp. All rights reserved. PAC VGA200 is a trademark of California Micro Devices Corp.
3/00
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
ABSOLUTE MAXIMUM RATINGS
Parameter
V
CC1
, V
CC2
, V
CC3
& V
CC4
supply voltage
D i o d e D 1 f o rwa rd c u rre n t
D C v o l ta g e a t i n p u ts :
V I D E O_ 1 , V I D E O_ 2 , V I D E O_ 3
T ER M_ 1 , T ER M_ 2 , T ER M_ 3
D D C_ I N 1 , D D C_ I N 2
D D C _ OU T 1 , D D C _ OU T 2
S Y N C_ I N 1 , S Y N C_ I N 2
Temperature:
Storage
Operating Ambient
Package power dissipation
-40 to +150
0 to +70
1.0
o
C
o
C
PRN299
Unit
V
uA
V
V
V
V
V
Rating
GND -0.5, +6.0
100
GND -0.5, V
CC1
+0.5
-6.0, +6.0
GND -0.5, V
CC2
+0.5
GND -0.5, V
CC3
+0.5
GND -0.5, V
CC4
+0.5
W
ELECTRICAL OPERATING CHARACTERISTICS
(over operating conditions unless specified other wise)
Symbol
Parameter
Conditions
MIN
TYP
MAX
UNIT
I
CC1
I
CC2, 3
I
CC4
V
CC1
s u p p l y c u rre n t
V
CC2
, V
CC3
s u p p l y c u rre n t
V
CC4
supply current
V
BIAS
R
T
V
IH
V
IL
V
OH
V
OL
R
b
, R
p
R
c
I
N
V
BIAS
open circuit voltage
V I D E O te r mi n a ti o n r e s i s ta n c e
R
T
r e s i s ta n c e ma tc h i n g
L o g i c H i g h i n p u t v o l ta g e
1
L o g i c L o w i n p u t v o l ta g e
1
L o g i c H i g h o u tp u t v o l ta g e
1
L o g i c L o w o u tp u t v o l ta g e
1
R e s i s to r v a l u e
V
CC 2
pull-down resistor
Input current
VID EO inputs
HSYNC, VSYNC inputs
V
CC1
= 5V; VID EO inputs at V
CC1
or GND
V
CC2
= V
CC3
= 5V
V
CC4
= 5V; SYNC inputs at GND or V
CC4
;
PWR_UP pin at V
CC4;
SYNC outputs unloaded
V
CC4
= 5V; SYNC inputs at 3.0V; PWR_UP
pin at V
CC4
; SYNC outputs unloaded
V
CC4
= 5V; PWR_UP input at GND ; SYNC
outputs unloaded
No external current drawn from V
BIAS
pin
71.25
V
CC4
= 5 .0 V
V
CC4
= 5 .0 V
I
OH
= -4mA, V
CC4
= 5.0V
I
OL
= 4mA, V
CC4
= 5.0V
PWR_UP, V
CC3
= 5.0V
V
CC2
= 3.0V
V
CC1
= 5V; V
IN
= V
CC1
or GND
V
CC4
= 5V; V
IN
= V
CC4
or GND
(V
CC2
- V
DDC_IN
) < 0.4V; V
DDC
_
OUT
= V
CC2
(V
CC2
- V
DDC_OUT
) < 0.4V; V
DDC
_
IN
= V
CC2
V
CC2
= 2.5V; V
S
= GND , I
DS
= 3mA
2.0
10
10
10
200
10
V
CC4
-0.8
75
1
78.75
2
0.8
4.4
0.5
0.5
1
1.5
0.4
2
3
±1
±1
10
10
0.15
uA
uA
uA
uA
uA
V
Ω
%
V
V
V
V
MΩ
MΩ
µA
µA
µA
µA
V
I
OFF
V
ON
C
IN
OFF state leakage current, level
shifting NFET
Voltage drop across level
shifting NFET when turned ON
Input capacitance
3
VID EO_1, VID EO_2, VID EO_3
t
PLH
t
PHL
t
r
, t
f
V
ESD
Note 1:
Note 2:
V
CC1
= 5 .0 V ; V
IN
= 2 .5 V ; me a s u re d a t 1 M H z
V
CC1
= 2.5V; V
IN
= 1.25V; measured at 1MHz
SYNC drivers L-H propagation delay C
L
= 5 0 p F; V
CC
= 5 V ; I n p u t t
r
a n d t
f
< 5 n s
SYNC drivers H-L propagation delay C
L
= 5 0 p F; V
CC
= 5 V ; I n p u t t
r
a n d t
f
< 5 n s
SYNC drivers output rise & fall times C
L
= 5 0 p F; V
CC
= 5 V ; I n p u t t
r
a n d t
f
< 5 n s
ESD withstand voltage
2, 3
V
CC1
= V
CC3
= V
CC4
= 5V
4.0
4.5
8
8
7
±8
pF
12
12
ns
ns
ns
kV
These parameter applies only to the HSYNC and VSYNC channels.
Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V
CC1
, V
CC3
and V
CC4
must be bypassed
to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse
is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins
are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD
protected to the industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015).
This parameter is guaranteed by design and characterization.
Note 3:
©2000 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3/00
CALIFORNIA MICRO DEVICES
Typical Connection Diagram
PRN299
A resistor may be necessary between the V
CC3
pin and ground if protection against a stream of ESD pulses is required while the
PAC VGA200 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into
the V
CC3
bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD
repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PAC VGA200 is in the power-up
state, an internal discharge resistor is connected to ground via an FET switch for this purpose.
For the same reason, V
CC1
and V
CC4
may also require bypass capacitor discharging resistors to ground if there are no other
components in the system to provide a discharge path to ground.
GNDA, the reference voltage for the 75R resistors is not connected internally to GNDD and should ideally be connected to the
ground of the video DAC IC.
Pins
24
ST
ANDAR
D PART ORDE RING INFORMATION
Package
Ordering Part Number
Style
Part Marking
QSOP
PACVGA200Q
When placing an order please specify desired shipping: Tubes or Tape & Reel.
© 2000 California Micro Devices Corp. All rights reserved.
3/00
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3
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