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74ALVC573PW-T

Description
Latching 3.3V oct D-type transp ltch 3S
Categorysemiconductor    Other integrated circuit (IC)   
File Size102KB,17 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric Compare View All

74ALVC573PW-T Overview

Latching 3.3V oct D-type transp ltch 3S

74ALVC573PW-T Parametric

Parameter NameAttribute value
MakerNXP
Product Categoryatresia
RoHSyes
Number of circuitsOctal
logical typeTTL
logic seriesALVC
polarityNon-Inverting
Input bias current (maximum value)0.2 uA
High level output current- 24 mA
Low level output current24 mA
propagation delay time2.2 ns @ 3.3 V
Supply voltage (maximum)3.6
Supply voltage (minimum)1.65 V
Maximum operating temperature+ 85 C
Minimum operating temperature- 40 C
Package/boxSOT-360
EncapsulationReel - 13 i
Installation styleSMD/SMT
74ALVC573
Octal D-type transparent latch; 3-state
Rev. 03 — 26 October 2007
Product data sheet
1. General description
The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for
each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input
and an outputs enable (OE) input are common to all latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this
condition, the latches are transparent, that is, a latch output will change each time its
corresponding D-input changes. When pin LE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of
pin LE.
When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins
Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of input pin OE does not affect the state of the latches.
The 74ALVC573 is functionally identical to the 74ALVC373, but has a different pin
arrangement.
2. Features
s
s
s
s
s
s
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Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V)
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A 115-A exceeds 200 V

74ALVC573PW-T Related Products

74ALVC573PW-T 74ALVC573D-T 935273687115 HCHP0705100PPM208K0.5%N0131E2
Description Latching 3.3V oct D-type transp ltch 3S Latching 3.3V oct D-type transp ltch 3S ALVC/VCX/A SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, SOT-764-1, MO-241, DHVQFN-20 Fixed Resistor, Metal Glaze/thick Film, 0.2W, 208000ohm, 150V, 0.5% +/-Tol, -100,100ppm/Cel, 0805,
Maximum operating temperature + 85 C - 85 °C 155 °C
Minimum operating temperature - 40 C - -40 °C -55 °C
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