INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4520
Dual 4-bit synchronous binary
counter
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
FEATURES
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4520 are high-speed Si-gate CMOS
devices and are pin compatible with the “4520” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4520 are dual 4-bit internally synchronous
binary counters with an active HIGH clock input (nCP
0
)
and an active LOW clock input (nCP
1
), buffered outputs
74HC/HCT4520
from all four bit positions (nQ
0
to nQ
3
) and an active HIGH
overriding asynchronous master reset input (nMR).
The counter advances on either the LOW-to-HIGH
transition of nCP
0
if nCP
1
is HIGH or the HIGH-to-LOW
transition of nCP
1
if nCP
0
is LOW. Either nCP
0
or nCP
1
may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ
0
to nQ
3
= LOW)
independent of nCP
0
and nCP
1
.
APPLICATIONS
•
Multistage synchronous counting
•
Multistage asynchronous counting
•
Frequency dividers
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
t
PHL
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay nCP
0
, nCP
1
to nQ
n
propagation delay nMR to nQ
n
maximum clock frequency
input capacitance
power dissipation capacitance per counter
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V 24
13
68
3.5
29
HCT
24
13
64
3.5
24
ns
ns
MHz
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
PIN DESCRIPTION
PIN NO.
1, 9
2, 10
3, 4, 5, 6
7, 15
8
11, 12, 13, 14
16
SYMBOL
1CP
0
, 2CP
0
1CP
1
, 2CP
1
1Q
0
to 1Q
3
1MR, 2MR
GND
2Q
0
to 2Q
3
V
CC
NAME AND FUNCTION
clock inputs (LOW-to-HIGH, edge-triggered)
clock inputs (HIGH-to-LOW, edge-triggered)
data outputs
asynchronous master reset inputs (active HIGH)
ground (0 V)
data outputs
positive supply voltage
74HC/HCT4520
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
FUNCTION TABLE
nCP
0
↑
L
↓
X
↑
H
X
Notes
nCP
1
H
↓
X
↑
L
↓
X
MR
L
L
L
L
L
L
H
74HC/HCT4520
MODE
counter advances
counter advances
no change
no change
no change
no change
Q
0
to Q
3
= LOW
Fig.4 Functional diagram.
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH clock transition
↓
= HIGH-to-LOW clock transition
Fig.5 Logic diagram (one counter).
Fig.6 Timing diagram.
December 1990
4
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
nCP
0
to nQ
n
propagation delay
nCP
1
to nQ
n
propagation delay
nMR to nQ
n
output transition time
+25
typ.
77
28
22
77
28
22
44
16
13
19
7
6
80
16
14
22
8
6
39
14
11
−28
−10
−8
14
5
4
19
58
69
−40
to
+85
max. min. max.
240
48
41
240
48
41
150
30
26
75
15
13
100
20
17
150
30
26
0
0
0
100
20
17
4.8
24
28
300
60
51
300
60
51
190
38
33
95
19
16
120
24
20
180
36
31
0
0
0
120
24
20
4.0
20
24
−40
to
+125
min.
max.
360
72
61
360
72
61
225
45
38
110
22
19
ns
74HC/HCT4520
TEST CONDITIONS
UNIT
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
WAVEFORMS
Fig.8
t
PHL
/ t
PLH
ns
Fig.8
t
PHL
ns
Fig.9
t
THL
/ t
TLH
ns
Fig.8
t
W
clock pulse width
HIGH or LOW
ns
Fig.7
t
W
master reset pulse width 120
HIGH
24
20
removal time
nMR to nCP
0
; nCP
1
set-up time
nCP
1
to nCP
0
;
nCP
0
to nCP
1
maximum clock pulse
frequency
0
0
0
80
16
14
6.0
30
35
ns
Fig.7
t
rem
ns
Fig.7
t
su
ns
Fig.8
f
max
MHz
Fig.7
December 1990
5
Embedded System
京公网安备 11010802033920号
EEWORLD
