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74AC244PC_Q

Description
Buffers and line drivers octal buf/line drv
Categorysemiconductor    logic   
File Size96KB,9 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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74AC244PC_Q Overview

Buffers and line drivers octal buf/line drv

74AC244PC_Q Parametric

Parameter NameAttribute value
MakerFairchild
Product CategoryBuffers and Line Drivers
RoHSno
logic series74AC
logical typeOctal Buffer and Line Drive
Number of channels per chip8
polarityNon-Inverting
Supply voltage (maximum)6 V
Supply voltage (minimum)2 V
Maximum operating temperature85 C
Minimum operating temperature- 40 C
Installation styleThrough Hole
Package/boxPDIP-20
EncapsulationTube
High level output current- 24 mA
Input bias current (maximum value)4 uA
Low level output current24 mA
Number of lines (input/output)3
Output type3-State
propagation delay time9 ns @ 3.3 V or 7 ns @ 5 V
74AC244 • 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs
November 1988
Revised November 1999
74AC244 • 74ACT244
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The AC/ACT244 is an octal buffer and line driver designed
to be employed as a memory address driver, clock driver
and bus-oriented transmitter/receiver which provides
improved PC board density.
Features
s
I
CC
and I
OZ
reduced by 50%
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
ACT244 has TTL-compatible inputs
Ordering Code:
Order Number
74AC244SC
74AC244SJ
74AC244MTC
74AC244PC
74ACT244SC
74ACT244SJ
74ACT244MSA
74ACT244MTC
74ACT244PC
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MSA20
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
Truth Tables
Inputs
OE
1
L
I
n
L
H
X
Inputs
OE
2
L
L
H
X
=
Immaterial
Z
=
High Impedance
FACT is a trademark of Fairchild Semiconductor Corporation.
Outputs
(Pins 12, 14, 16, 18)
L
H
Z
Outputs
I
n
L
H
X
(Pins 3, 5, 7, 9)
L
H
Z
Connection Diagram
L
H
© 1999 Fairchild Semiconductor Corporation
DS009943
www.fairchildsemi.com

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