Philips Semiconductors
Product specification
Quad 2-input NAND gate
FEATURES
•
Wide supply voltage range from 1.65 to 3.6 V
•
3.6 V tolerant inputs/outputs
•
CMOS low power consumption
•
Direct interface with TTL levels (2.7 to 3.6 V)
•
Power-down mode
•
Latch-up performance exceeds 250 mA
•
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay inputs
nA, nB to output nY
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
power dissipation capacitance per buffer V
CC
= 3.3 V; notes 1 and 2
DESCRIPTION
74ALVC00
The 74ALVC00 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
The 74ALVC00 provides the 2-input NAND function.
TYPICAL
2.8
2.1
2.6
2.1
3.5
28
ns
ns
ns
ns
UNIT
pF
pF
2003 May 14
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
handbook, halfpage
1A
1
VCC
14
13
12
4B
4A
4Y
B
3B
3A
handbook, halfpage
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
Top view
GND
8
3Y
A
Y
MNA211
GND
(1)
11
10
9
MNA950
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN14.
Fig.3 Logic diagram (one gate).
handbook, halfpage
handbook, halfpage
1
2
&
3
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
&
6
2Y
6
5
3Y
8
9
10
&
8
4Y
11
12
&
11
MNA212
13
MNA246
Fig.4 Function diagram.
Fig.5 IEC logic symbol.
2003 May 14
4
Philips Semiconductors
Product specification
Quad 2-input NAND gate
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
supply voltage
input voltage
output voltage
operating ambient temperature
input rise and fall times
V
CC
= 1.65 to 2.7 V
V
CC
= 2.7 to 3.6 V
V
CC
= 1.65 to 3.6 V
V
CC
= 0 V; Power-down mode
CONDITIONS
0
0
0
−40
0
0
MIN.
1.65
74ALVC00
MAX.
3.6
3.6
V
CC
3.6
+85
20
10
V
V
V
V
UNIT
°C
ns/V
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
T
stg
P
tot
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When V
CC
= 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
3. For SO14 packages: above 70
°C
derate linearly with 8 mW/K.
For TSSOP14 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
derate linearly with 4.5 mW/K.
PARAMETER
supply voltage
input diode current
input voltage
output diode current
output voltage
output source or sink current
V
CC
or GND current
storage temperature
power dissipation per package
T
amb
=
−40
to +125
°C;
note 3
V
O
> V
CC
or V
O
< 0
notes 1 and 2
Power-down mode; note 2
V
O
= 0 to V
CC
V
I
< 0
CONDITIONS
−
−0.5
−
−0.5
−0.5
−
−
−65
−
MIN.
−0.5
MAX.
+4.6
−50
+4.6
±50
+4.6
±50
±100
+150
500
V
mA
V
mA
V
mA
mA
°C
mW
UNIT
V
CC
+ 0.5 V
2003 May 14
5
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