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74LVX74MTCX_NL

Description
Trigger Dl D-type flip-flop
Categorylogic    logic   
File Size309KB,9 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74LVX74MTCX_NL Overview

Trigger Dl D-type flip-flop

74LVX74MTCX_NL Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP14,.25
Contacts14
Reach Compliance Codecompli
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G14
JESD-609 codee3
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su50000000 Hz
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of digits1
Number of functions2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Su15 ns
propagation delay (tpd)22 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width4.4 mm
minfmax80 MHz
Base Number Matches1
74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
February 2008
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
Features
Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and
dynamic threshold performance
Q HIGH
Ordering Information
Order
Number
74LVX74M
74LVX74SJ
74LVX74MTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1993 Fairchild Semiconductor Corporation
74LVX74 Rev. 1.4.0
www.fairchildsemi.com
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