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74ACTQ273PC_Q

Description
Trigger oct D-type flip-flop
Categorysemiconductor    Other integrated circuit (IC)   
File Size249KB,10 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

74ACTQ273PC_Q Overview

Trigger oct D-type flip-flop

74ACTQ273PC_Q Parametric

Parameter NameAttribute value
MakerFairchild
RoHSno
Number of circuitsOctal
logic series74ACT
logical typeD-Type Flip-Flops
polarityNon-Inverting
input typeSingle-Ended
Output typeSingle-Ended
propagation delay time8.5 ns @ 5 V
High level output current- 24 mA
Low level output current24 mA
Supply voltage (maximum)5.5 V
Maximum operating temperature85 C
Installation styleThrough Hole
Package/boxPDIP-20
EncapsulationTube
Minimum operating temperature- 40 C
Supply voltage (minimum)4.5 V
74ACTQ273 Quiet Series Octal D-Type Flip-Flop
May 2007
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
Features
I
CC
reduced by 50%
Guaranteed simultaneous switching noise level and
tm
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) input load
and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each
D-type input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-
flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output
only is required and the Clock and Master Reset are
common to all storage elements.
The ACTQ utilizes Fairchild Quiet Series™ technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTO™ output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
Buffered common clock and asynchronous master
reset
Outputs source/sink 24mA
4kV minimum ESD immunity
Ordering Information
Order Number
74ACTQ273SC
74ACTQ273SJ
74ACTQ273MTC
Package
Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
Pin Names
D
0
–D
7
MR
CP
Q
0
–Q
7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1989 Fairchild Semiconductor Corporation
74ACTQ273 Rev. 1.4
www.fairchildsemi.com

74ACTQ273PC_Q Related Products

74ACTQ273PC_Q 74ACTQ273SJ_Q
Description Trigger oct D-type flip-flop Trigger oct D-type flip-flop
Maker Fairchild Fairchild
RoHS no no
Number of circuits Octal Octal
logic series 74ACT 74ACT
logical type D-Type Flip-Flops D-Type Flip-Flops
polarity Non-Inverting Non-Inverting
input type Single-Ended Single-Ended
Output type Single-Ended Single-Ended
propagation delay time 8.5 ns @ 5 V 8.5 ns @ 5 V
High level output current - 24 mA - 24 mA
Low level output current 24 mA 24 mA
Supply voltage (maximum) 5.5 V 5.5 V
Maximum operating temperature 85 C 85 C
Installation style Through Hole SMD/SMT
Package/box PDIP-20 SOP-20
Encapsulation Tube Tube
Minimum operating temperature - 40 C - 40 C
Supply voltage (minimum) 4.5 V 4.5 V
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