EEWORLDEEWORLDEEWORLD

Part Number

Search

531UB703M000DGR

Description
CMOS/TTL Output Clock Oscillator, 703MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric View All

531UB703M000DGR Overview

CMOS/TTL Output Clock Oscillator, 703MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531UB703M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency703 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
PC104 screen display
The PC104 used is DOS6.22. I found that sometimes the screen would freeze when I turned it on. It was normal after restarting. What is the reason?...
ljy00012 Embedded System
A great man's understanding of analog circuits
A great man's understanding of analog circuits [url=http://bbs.ednchina.com/ShowTopic.aspx?id=31312][color=#216b8a][/color][/url]...
songbo Analog electronics
Ask Googleman, CE6 problem
I would like to ask Googleman, do you have the S3C2440 BSP for CE6? I downloaded one from www.driverdevelop.com, but it can't create the OS normally. I can't even get past the first step of New. Thank...
aqiraby Embedded System
Analysis of ZIGBEE report mechanism
ZIGBEE provides a report mechanism (now only learned send, receive has not been learned) The main purpose is to implement the report function of the attribute, that is, to provide a mechanism for sync...
灞波儿奔 RF/Wirelessly
Dear experts, I have a question. How can I reduce the size of the program compiled by uclinux-elf-gcc?
From EEWORLD cooperation group: arm linux fpga embedded 0 (49900581) group owner: wangkj all experts. Ask a question. The program I compiled with uclinux-elf-gcc is very large. It is 1M. My kernel plu...
梦之路 FPGA/CPLD
ADS7841 Application Circuit Design Guide - Personal Understanding
Recently, I developed a new product using the ADS7841 sampling chip. I feel that this sampling chip is good, simple and easy to use. I read the DATASHEET and now I share my personal understanding with...
eeleader Industrial Control Electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 730  957  1598  1777  1094  15  20  33  36  23 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号