Latch-Up Current..................................................... >200 mA
Maximum Ratings
[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
....................................... −65
°
C to +150
°
C
Ambient Temperature with
Power Applied....................................................
−55
°
C to +125
°
C
Supply Voltage to Ground Potential
.................−0.5V
to +7.0V
DC Voltage Applied to Outputs
in High Z State
............................................−0.5V
to V
CC
+ 0.5V
DC Input Voltage..........................................−0.5V to V
cc
+0.5V
Operating Range
Range
Commercial
Industrial
[2]
Military
Ambient
Temperature
0
°
C to +70
°
C
−40
°
C to +85
°
C
−55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Note:
1. The Voltage on any input or I/O pin cannot exceed the power pin during
power-up.
2. T
A
is the “instant on” case temperature.
Document #: 38-06015 Rev. *A
Page 2 of 20
CY7C4261
CY7C4271
Pin Definitions
Signal Name
D
0−8
Q
0−8
WEN1
Description
Data Inputs
Data Outputs
Write Enable 1
I/O
I
O
I
Data Inputs for 9-bit bus.
Data Outputs for 9-bit bus.
The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition
of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-off-
set register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset
register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO. PAE is synchronized to RCLK.
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed
into the FIFO. PAF is synchronized to WCLK.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Description
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
I
I
RCLK
Read Clock
I
EF
FF
PAE
PAF
RS
OE
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
O
O
O
O
I
I
Document #: 38-06015 Rev. *A
Page 3 of 20
CY7C4261
CY7C4271
Electrical Characteristics
Over the Operating Range
[3]
7C4261/71−
10
Parameter
V
OH
V
OL
V
IH
V
IH
V
IL
I
IX
I
OZL
I
OZH
I
CC1[4]
I
SB[5]
Description
Test Conditions
Min.
2.4
0.4
2.0
2.2
−0.5
V
CC
= Max.
OE
>
V
IH
,
V
SS
< V
O
< V
CC
Com’l
Ind/Mil
Com’l
Ind/Mil
−10
−10
V
CC
V
CC
0.8
+10
+10
35
40
10
15
2.0
2.2
−0.5
−10
−10
Max.
Output HIGH Voltage V
CC
= Min.,
I
OH
=
−2.0
mA
Output LOW Voltage
Input HIGH Voltage
(comm./ind.)
Input HIGH Voltage
(military)
Input LOW Voltage
Input Leakage
Current
Output OFF,
High Z Current
Active Power Supply
Current
Average Standby
Current
V
CC
= Min.,
I
OL
= 8.0 mA
7C4261/71−
15
Min.
2.4
0.4
V
CC
V
CC
0.8
+10
+10
35
40
10
15
2.0
2.2
−0.5
−10
−10
Max.
7C4261/71−
25
Min.
2.4
0.4
V
CC
V
CC
0.8
+10
+10
35
40
10
15
2.0
2.2
−0.5
−10
−10
Max.
7C4261/71−
35
Min.
2.4
0.4
V
CC
V
CC
0.8
+10
+10
35
40
10
15
Max.
Unit
V
V
V
V
V
µA
µA
mA
mA
mA
mA
Capacitance
[6]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
5
7
Unit
pF
pF
AC Test Loads and Waveforms
[7, 8]
R11.1K
Ω
5V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
420
Ω
OUTPUT
R2
680Ω
3.0V
GND
≤
3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤
3 ns
4261–5
4261–4
1.91V
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20Mhz, while data inputs
switch at 10 MHz. Outputs are unloaded. Icc1(typical) = (20mA+(freq-20MHz)*(0.7mA/MHz))
5. All inputs = V
CC
– 0.2V, except WCLK and RCLK (which are switching at frequency = 20 MHz). All outputs are unloaded.
6. Tested initially and after any design or process changes that may affect these parameters.
7. C
L
= 30 pF for all AC parameters except for t
OHZ
.
8. C
L
= 5 pF for t
OHZ
.
Document #: 38-06015 Rev. *A
Page 4 of 20
CY7C4261
CY7C4271
Switching Characteristics
Over the Operating Range
7C4261/71
−10
Parameter
t
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
SKEW1
t
SKEW2
Description
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-Up Time
Data Hold Time
Enable Set-Up Time
Enable Hold Time
Reset Pulse Width
[9]
Reset Set-Up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low Z
[10]
Output Enable to Output Valid
Output Enable to Output in High Z
[10]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
Skew Time between Read Clock and Write
Clock for Almost-Empty Flag and Almost-Full
Flag
5
10
0
3
3
7
7
8
8
8
8
6
15
2
10
4.5
4.5
3
0.5
3
0.5
10
8
8
10
0
3
3
8
8
10
10
10
10
10
18
Min.
Max.
100
8
2
15
6
6
4
1
4
1
15
10
10
15
0
3
3
12
12
15
15
15
15
12
20
7C4261/71
−15
Min.
Max.
66.7
10
2
25
10
10
6
1
6
1
25
15
15
25
0
3
3
15
15
20
20
20
20
7C4261/71
−25
Min.
Max.
40
15
2
35
14
14
7
2
7
2
35
20
20
35
7C4261/71
−
35
Min.
Max.
28.6
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
9. Pulse widths less than minimum values are not allowed.
10. Values guaranteed by design, not currently tested.
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