ISPLSI2032V-60LT44I datasheet, PDF

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ISPLSI2032V-60LT44I: DescriptionEE PLD, 20ns, 32-Cell, CMOS, PQFP44, TQFP-44; CategoryProgrammable logic devices Programmable logic; File Size115KB，12 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ISPLSI2032V-60LT44I Overview

EE PLD, 20ns, 32-Cell, CMOS, PQFP44, TQFP-44

ISPLSI2032V-60LT44I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	QFP
package instruction	TQFP-44
Contacts	44
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	YES
maximum clock frequency	51.3 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G44
JESD-609 code	e0
JTAG BST	NO
length	10 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	32
Number of macro cells	32
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP44,.47SQ,32
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Programmable logic type	EE PLD
propagation delay	20 ns
Certification status	Not Qualified
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm
Base Number Matches	1

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ispLSI 2032V

3.3V High Density Programmable Logic

Features

• HIGH DENSITY PROGRAMMABLE LOGIC

1000 PLD Gates

32 I/O Pins, Two Dedicated Inputs

32 Registers

High Speed Global Interconnect

Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• 3.3V LOW VOLTAGE 2032 ARCHITECTURE

Input Bus

Functional Block Diagram

Output Routing Pool (ORP)

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

Electrically Erasable and Reprogrammable

Non-Volatile

100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability Using Boundary

Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of

Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

max

= 100 MHz Maximum Operating Frequency

= 7.5 ns Propagation Delay

D Q

GLB

Logic

Array

D Q

0139Bisp/2000

Description

The ispLSI 2032V is a High Density Programmable Logic

Device that can be used in both 3.3V and 5V systems.

The device contains 32 Registers, 32 Universal I/O pins,

two Dedicated Input Pins, three Dedicated Clock Input

Pins, one dedicated Global OE input pin and a Global

Routing Pool (GRP). The GRP provides complete

interconnectivity between all of these elements. The

ispLSI 2032V features in-system programmability through

the Boundary Scan Test Access Port (TAP). The ispLSI

2032V offers non-volatile reprogrammability of the logic,

as well as the interconnect to provide truly reconfigurable

systems.

The basic unit of logic on the ispLSI 2032V device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. A7 (see Figure 1). There are a total of eight GLBs in the

ispLSI 2032V device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

—

Enhanced Pin Locking Capability

Three Dedicated Clock Input Pins

Synchronous and Asynchronous Clocks

Programmable Output Slew Rate Control

Flexible Pin Placement

Optimized Global Routing Pool Provides Global

Interconnectivity

to change without notice.

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2032v_10

Input Bus

— Interfaces With Standard 5V TTL Devices

— 60 mA Typical Active Current

— Fuse Map Compatible with 5V ispLSI 2032

D Q

Output Routing Pool (ORP)

Global Routing Pool

(GRP)

—

ISPLSI2032V-60LT44I Related Products

	ISPLSI2032V-60LT44I	ISPLSI2032V-80LJ44	ISPLSI2032V-60LJ44I	ISPLSI2032V-60LT44	ISPLSI2032V-100LT44	ISPLSI2032V-100LJ44	ISPLSI2032V-60LJ44	ISPLSI2032V-80LT44
Description	EE PLD, 20ns, 32-Cell, CMOS, PQFP44, TQFP-44	EE PLD, 15ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44	EE PLD, 20ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44	EE PLD, 20ns, 32-Cell, CMOS, PQFP44, TQFP-44	EE PLD, 12ns, 32-Cell, CMOS, PQFP44, TQFP-44	EE PLD, 12ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44	EE PLD, 20ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44	EE PLD, 15ns, 32-Cell, CMOS, PQFP44, TQFP-44
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Lattice	Lattice	Lattice	Lattice	Lattice	Lattice	Lattice	Lattice
Parts packaging code	QFP	LCC	LCC	QFP	QFP	LCC	LCC	QFP
package instruction	TQFP-44	PLASTIC, LCC-44	PLASTIC, LCC-44	TQFP-44	TQFP-44	PLASTIC, LCC-44	PLASTIC, LCC-44	TQFP-44
Contacts	44	44	44	44	44	44	44	44
Reach Compliance Code	unknown	unknown	unknown	unknown	compliant	compliant	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Other features	YES	YES	YES	YES	YES	YES	YES	YES
maximum clock frequency	51.3 MHz	64.5 MHz	51.3 MHz	51.3 MHz	83.3 MHz	83.3 MHz	51.3 MHz	64.5 MHz
In-system programmable	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	S-PQFP-G44	S-PQCC-J44	S-PQCC-J44	S-PQFP-G44	S-PQFP-G44	S-PQCC-J44	S-PQCC-J44	S-PQFP-G44
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
JTAG BST	NO	NO	NO	NO	NO	NO	NO	NO
length	10 mm	16.5862 mm	16.5862 mm	10 mm	10 mm	16.5862 mm	16.5862 mm	10 mm
Humidity sensitivity level	3	3	3	3	3	3	3	3
Number of I/O lines	32	32	32	32	32	32	32	32
Number of macro cells	32	32	32	32	32	32	32	32
Number of terminals	44	44	44	44	44	44	44	44
Maximum operating temperature	85 °C	70 °C	85 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	QCCJ	QCCJ	QFP	QFP	QCCJ	QCCJ	QFP
Encapsulate equivalent code	QFP44,.47SQ,32	LDCC44,.7SQ	LDCC44,.7SQ	QFP44,.47SQ,32	QFP44,.47SQ,32	LDCC44,.7SQ	LDCC44,.7SQ	QFP44,.47SQ,32
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	CHIP CARRIER	CHIP CARRIER	FLATPACK	FLATPACK	CHIP CARRIER	CHIP CARRIER	FLATPACK
Peak Reflow Temperature (Celsius)	240	225	240	240	240	225	225	240
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	20 ns	15 ns	20 ns	20 ns	12 ns	12 ns	20 ns	15 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	J BEND	J BEND	GULL WING	GULL WING	J BEND	J BEND	GULL WING
Terminal pitch	0.8 mm	1.27 mm	1.27 mm	0.8 mm	0.8 mm	1.27 mm	1.27 mm	0.8 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30
width	10 mm	16.5862 mm	16.5862 mm	10 mm	10 mm	16.5862 mm	16.5862 mm	10 mm
Base Number Matches	1	1	1	1	1	1	1	1

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