CD4011B, CD4012B, CD4023B Types
COS/MOS NAND Gates
High-Voltage Types (20-Volt Rating)
Quad 2 Input - CD4011B'
Dual 4 Input - CD4012B
Triple 3 Input - CD4023B
RCA-CD40118, CD40128. and CD40238
NAND gates provide the system designer
with direct implementation of the NAND
function and supplement the eXisting family
of COS/MOS gates. All Inputs and outputs
are buffered.
The CD4011 B. CD4012B. and CD4023B
types are supplied in 14-lead hermetic dual-
in-line ceramic packages (D and F suffixes).
14-lead dual-in-line plas,tic packages (E'suf-
fix). 14-lead ceramic flat packages (K suffiX).
and In chip form (H suffix).
Features:
• Propagation delay time = 60 ns (typ.l at
CL=50pF, VDD= 10V
• Buffered inputs and outputs
• Standardized symmetrical output characteristics
• Maximum input current of 1 JJ.A at 18 V
over full package temperature range;
100 nA at 18 V and 25
0
C
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package temperature
range:
1 Vat VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
• Meets all requirements of jEDEC Tentative
Standard No.13A, "Standard Specifications
for Description of "B" Series CMOS Devices"
92CS-24763
CD4011B
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS,
Ahsolllte·MaxlIlIlIlII Values
DC SUPPLY·VOLTAGE RANGE. (V DD )
(Volwgt:s Il'fell'lIcecilo VSS T"IInll'dl)
INPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT, ANY ONE INPUT
-05 to ,20 V
-051OVoD '05V
±10 mA
Voo
POWER DISSIPATION PER PACKAGE (PO)
For T A
401o 'GOoC (PACKAGE TYPE E)
500mW
For T A
.GO
10
'85
0
C (PACKAGE TYPE E)
o'~rdll'
LII'early al 12 mW/oC 10 200 mW
For T A
5510 I 1000C (PACKAGE TYPES D,Fl
500mW
ForTA
'10010 I 125"C IPACKAGE TYPES
0,
F)
De",te Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TIlANSISTOR
FOR TA
FULL PACKAGE TEMPERATURE RANGE (All PdckdIJI' Typ"s)
100mW
OPERATING TEMPERA rURE RANGE (TA)
PACKAGE TYPES D,
F, H
- 55 10
t
125 0 C
PACKAGE TYPE E
-,40 to +85
0
C
STORAGE TEMPERATURE RANGE
IT,,q)
-65 10
t
150 0
C
LEAD TEMPERATURE IDUFlING SQL[JERING)
At
Chc;,I ..IIlCP
1
1
16 1 3?
1I1Lil
(1 59 • 0 79
I1lln)
1I0in
Ld''''
tOI
10'\
ITldX
VSS
7
••
~
NC
CD4012B
92CS-24"9
FUNCTIONAL DIAGRAM
RECOMMENDED OPERATING CONDITIONS
For maximum reliability. nominal operating conditions should be selected so that
operation is always within the fol/owing ranges:
CHARACTERISTIC
MIN.
Supply·Voltage Range (For T A
=
Full Package
Temperature Range)
3
LIMITS
MAX.
18
UNITS
14 Voo
V
TERMINAL ASSIGNMENTS
VSS
A
B
I.
2
3
.·W
[)
J'AB
14
13
12
II
VOO
J'ABCO
t.
2
t4
13
II
V
OO
..~
1.*4
_VOu
2
13
G
3
12 -
I:~·
CD4023B
92C5-
FUNCTIONAL DIAGRAM
24761
..
10
9 -
B
hf·lH
lOU
F
NC
4
I
10
9
NC
TOP VIEW
92CS.244~4AI
10' - L·rn
-
J.Ed~
Vss
TOP
VIEW
E
Vss
-C
TOP
VIEW
NC'NO CONNECTtON
CD4011B
CD4012B
CD4023B
74
II
CD4011 B, CD4012B, CD4023B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
Valuelat -55, +25, +125 Apply to D,F ,H Packages
CONDITIONS
CHARACTER-
t - - - - r - - - , r - - - I
Valuel at
-40,
+25, +85 APpIYr-t_o_E _
~~
_ _
-t
_
ISTIC
Quiescent Device
1----+-:-!-~f-:7"'"+_-__+--+--+--+_-_+_:__:___+-__;
Current,
100 Max.
Output Low
(Sink) Current
IOL Min
Output High
(Source)
Current,
IOH Min.
Output Voltage'
Lew·Level,
VOL Max.
mA
15
INPUT VOLTAGE (V1)- V
20
Fig.
1 -
Typical voltage transfer characteflstics.
10': AMBIENT TEMPERATURE
(TA'-20·C
V
Output Voltage'
Hlgh·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
V
Fig.2
-
10
102
INPUT FREOUENCY " 1 ) - kH,
..
4
a
10'
2:
4
II
10 4
t2C'~I8'05
Typical power diSSipation characteflstics.
±10- S
±O.l
~A
DRAIN-TO-SOURCE VOLTAGE (YDSI-Y
Flg.3
-
Typical output low (sink) current
charadteristics.
DRAIN-TO-SOURCE VOLTAGE (Vos)-V
DRAIN-TO-\SOURCE VOLTAGE (VDS)-V
DRAIN-TO-SOURCE \IOLTAGE IVDsI-V
IICt-MSI,.,.
Fig.4
-
Minimum output low (sink) current
characteristics.
Fig.5
-
Typical output high (source) current
characteristics.
Fig.
6 -
Mintmum output high (source) current
characteristics.
_________________________________________________________________________ 75
CD40118, CD40128, CD40238 Typ
s
VOO
14
11131
fiOD
fi'oo
4ss
NETWORK
I(B,6J31~
3
(10,4,111
2'9,5,121
LOGIC OIAGRAM
4ss
r
p
11131
n
*
BY COS
I
MOS ARE PROTECTEO
ALL INPUTS
PROTECT ION
NETWORK
*
BY
COSIMOS
ARE PROTECTED
ALL INPUTS
PROTECTION
I OF 4 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS
FOR OTHER GATES
I
F,g.l- Schematic and logic diagrams for
CD401 18.
Fig.8
-
Schematic and logic diagrams for
CD40128.
3II'"I~
4'2,121
6'9,101
5'B,I31
4*(2.121
LOGIC
DIAGRAM
*
BY
COSIMOS
ARE PROTECTED
ALL INPUTS
PROTECTION
NETWORK
I OF 3 GATES (NUMBERS IN
PARENTHESES ARE TERMINAL
NUMBERS FOR OTHER GATES I
g.
TYP.
60
LOAO CAPACITANCE
70
I~I-
pF
7
Fig.
10
-
Typical propagation delay time per gate
as a function of load capacitance.
.
vss
Fig.
9 -
Schematic and logiC diagrams for
CD40238.
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA
=
25'C; Input t" tf= 20ns, CL
=
50pF, R L
=
200kf2
ALL TYPES
LIMITS
MAX.
TEST CONDITIONS
CHARACTER ISTIC
V DD
VOLTS
Propagation Delay Time,
tpHL. tPLH
UNITS
Transition Time.
tTHL. tTLH
Input Capacitance. CI N
Any Input
5
10
15
5
10
15
125
60
45
100
50
40
5
250
120
90
200
100
80
7.5
ns
ns
LOAD CAPACITANCE (CL'- pF
pF
Fig.
11 -
Typical transition time as a function of
load capacitance.
76 _______________________________________________________________________
II
CD4011B, CD4012B, CD4023B Types
INPUTS
o
Vss
V,-
vtL
00
INPUTQVOO
• OUTPUTS
VOO
INPUO'
'00
~
l
VSS
NOTE
TEST ANY CONBINATION
OF INPUTS
~
VSS
~"
~::~:;I~~~~~S
TO BOTH Voo AND VSS
CONNECT ALL UNUSEO
INPUTS TO EITHER
Voo OR Vss
Vss
Fig.
13 -
Input-voltage test CircUIt.
Fig.
12 -
Quiescent-device-current test circuit.
Fig.
14 -
Input-current test circuIt.
CHIP PHOTOGRAPHS
Dimensions and Pad Layouts
0
60-
10
1
I
20
1
30
-I
40
I
50
I
60
I
69
I
e
CD4011BH
l
50-
40-
42-50
(1067-1270)
30-
1
57-65
U 448-1651)
10-
J
CD4012BH
DimenSions In parentheses are In mtl"meters and
are derived from the baSIC Inch dimenSions as in-
dicated. Grid graduations are In mils
(10-
3 Inch).
The photographs and dimenSions of each
COS/MOS
chip represent a chip when It IS part of the wafer.
When the waferts cut Into ChiPS, the cleavage angles
with respect to the face of
are 57 0 Instead of
the chip. Therefore, the Isolated chip IS acruallv
7 mtls
(0
17mm) larger In both dimenSIOns
9oo
CD4023BH
___________________________________________________________________________ 77
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