DISCRETE SEMICONDUCTORS
DATA SHEET
PMBF170
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a SOT23
envelope. Designed for use as a
Surface Mounted Device (SMD) in
thin and thick-film circuits with
applications in relay, high-speed and
line transformer drivers.
FEATURES
•
Direct interface to C-MOS, TTL,
etc.
•
High-speed switching
•
No secondary breakdown
QUICK REFERENCE DATA
Drain-source voltage
Gate-source voltage (open drain)
Drain current (DC)
Total power dissipation up
to T
amb
= 25
°C
Drain-source on-resistance
I
D
= 200 mA; V
GS
= 10 V
Transfer admittance
I
D
= 200 mA; V
DS
= 10 V
PINNING - SOT23
1
2
3
= gate
= source
= drain
V
DS
±
V
GSO
I
D
P
tot
R
DS(on)
| Y
fs
|
max.
max.
max.
max.
typ.
max.
min.
typ.
PMBF170
60 V
20 V
250 mA
300 mW
2.5
Ω
5.0
Ω
100 mS
200 mS
Marking code:
PMBF170 =
P
KX
PIN CONFIGURATION
handbook, halfpage
3
handbook, 2 columns
d
g
1
Top view
2
MSB003
MBB076 - 1
s
Fig.1 Simplified outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage
Gate-source voltage (open drain)
Drain current (DC)
Drain current (peak)
Total power dissipation up to
T
amb
= 25
°C
(note 1)
Storage temperature range
Junction temperature
THERMAL RESISTANCE
From junction to ambient (note 1)
From junction to ambient (note 2)
Notes
1. Mounted on ceramic substrate measuring 10 mm
×
8 mm
×
0.7 mm.
2. Mounted on printed-circuit board.
R
th j-a
R
th j-a
=
=
V
DS
±
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
max.
max.
max.
max.
max.
max.
max.
PMBF170
60 V
20 V
250 mA
500 mA
300 mW (note 1)
250 mW (note 2)
150
°C
−65
to
+150 °C
430 K/W
500 K/W
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified
Drain-source breakdown voltage
I
D
= 10
µA;
V
GS
= 0
Drain-source leakage current
V
DS
= 25 V; V
GS
= 0
V
DS
= 48 V; V
GS
= 0
Gate-source leakage current
V
GS
= 15 V; V
DS
= 0
Gate-source cut-off voltage
I
D
= 1 mA; V
DS
= V
GS
Drain-source on-resistance
I
D
= 200 mA; V
GS
= 10 V
Transfer admittance
I
D
= 200 mA; V
DS
= 10 V
Input capacitance
V
DS
= 10 V; V
GS
= 0 V; f = 1 MHz
Output capacitance
V
DS
= 10 V; V
GS
= 0 V; f = 1 MHz
Feedback capacitance
V
DS
= 10 V; V
GS
= 0 V; f = 1 MHz
Switching times
V
GS
= 0 to 10 V; I
D
= 200 mA ; V
DD
= 50 V
t
on
t
off
max.
max.
C
rss
typ.
max.
C
oss
typ.
max.
C
iss
typ.
max.
Y
fs
min.
typ.
R
DS(on)
typ.
max.
V
GS(th)
min.
max.
I
GSS
max.
I
DSS
I
DSS
max.
max.
V
(BR) DSS
min.
typ.
PMBF170
60 V
90 V
500 nA
1
µA
10 nA
0.8 V
3.0 V
2.5
Ω
5.0
Ω
100 mS
200 mS
25 pF
40 pF
22 pF
30 pF
6 pF
10 pF
10 ns
15 ns
April 1995
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF170
handbook, halfpage
VDD = 50 V
handbook, halfpage
90 %
INPUT
10 %
10 V
0V
ID
50
Ω
MSA631
90 %
OUTPUT
10 %
ton
toff
MBB692
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
April 1995
5
京公网安备 11010802033920号
EEWORLD
