RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
PM7382
FREEDM™-32P256
FRAME ENGINE AND DATALINK
MANAGER 32P256
DATA SHEET
RELEASED
ISSUE 3: AUGUST 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
PUBLIC REVISION HISTORY
Issue No.
Issue 1
Issue 2
Issue 3
Issue Date
April 11, 2001
August 13, 2001
August 22, 2001
Details of Change
Created Document.
Changed Status from Advance to Released
Added patent information to legal footer.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
i
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
CONTENTS
1
2
3
4
5
6
7
8
FEATURES...............................................................................................1
APPLICATIONS........................................................................................4
REFERENCES .........................................................................................5
BLOCK DIAGRAM....................................................................................6
DESCRIPTION .........................................................................................7
PIN DIAGRAM ........................................................................................10
PIN DESCRIPTION ................................................................................ 11
FUNCTIONAL DESCRIPTION ...............................................................36
8.1
8.2
8.3
HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL
(H-MVIP) ......................................................................................36
HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........36
RECEIVE CHANNEL ASSIGNER ................................................37
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
LINE INTERFACE TRANSLATOR (LIT) ........................39
LINE INTERFACE..........................................................39
PRIORITY ENCODER ...................................................40
CHANNEL ASSIGNER ..................................................40
LOOPBACK CONTROLLER .........................................41
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...41
8.4.1
8.4.2
HDLC PROCESSOR .....................................................42
PARTIAL PACKET BUFFER PROCESSOR ..................42
8.5
RECEIVE DMA CONTROLLER ...................................................44
8.5.1
8.5.2
DATA STRUCTURES ....................................................44
DMA TRANSACTION CONTROLLER...........................54
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
8.5.3
8.5.4
8.5.5
8.6
WRITE DATA PIPELINE/MUX .......................................54
DESCRIPTOR INFORMATION CACHE ........................54
FREE QUEUE CACHE ..................................................55
PCI CONTROLLER......................................................................55
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
MASTER MACHINE ......................................................56
MASTER LOCAL BUS INTERFACE..............................58
TARGET MACHINE .......................................................59
CBI BUS INTERFACE ...................................................61
ERROR / BUS CONTROL .............................................61
8.7
TRANSMIT DMA CONTROLLER.................................................61
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
DATA STRUCTURES ....................................................62
TASK PRIORITIES ........................................................74
DMA TRANSACTION CONTROLLER...........................74
READ DATA PIPELINE..................................................74
DESCRIPTOR INFORMATION CACHE ........................74
FREE QUEUE CACHE ..................................................75
8.8
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER75
8.8.1
8.8.2
TRANSMIT HDLC PROCESSOR..................................75
TRANSMIT PARTIAL PACKET BUFFER PROCESSOR76
8.9
TRANSMIT CHANNEL ASSIGNER .............................................78
8.9.1
8.9.2
8.9.3
8.9.4
LINE INTERFACE TRANSLATOR (LIT) ........................80
LINE INTERFACE..........................................................80
PRIORITY ENCODER ...................................................81
CHANNEL ASSIGNER ..................................................81
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
8.10
8.11
8.12
9
PERFORMANCE MONITOR .......................................................82
JTAG TEST ACCESS PORT INTERFACE...................................82
PCI HOST INTERFACE ...............................................................82
NORMAL MODE REGISTER DESCRIPTION ........................................87
9.1
PCI HOST ACCESSIBLE REGISTERS .......................................87
10
PCI CONFIGURATION REGISTER DESCRIPTION ............................250
10.1
PCI CONFIGURATION REGISTERS.........................................250
11
TEST FEATURES DESCRIPTION .......................................................261
11.1
11.2
TEST MODE REGISTERS ........................................................261
JTAG TEST PORT .....................................................................262
11.2.1
11.2.2
IDENTIFICATION REGISTER .....................................263
BOUNDARY SCAN REGISTER ..................................263
12
OPERATIONS ......................................................................................280
12.1
12.2
TOCTL CONNECTIONS ............................................................280
JTAG SUPPORT........................................................................280
13
FUNCTIONAL TIMING .........................................................................287
13.1
13.2
13.3
13.4
13.5
13.6
RECEIVE H-MVIP LINK TIMING ...............................................287
TRANSMIT H-MVIP LINK TIMING.............................................288
RECEIVE NON H-MVIP LINK TIMING ......................................289
TRANSMIT NON H-MVIP LINK TIMING ....................................291
PCI INTERFACE ........................................................................292
BERT INTERFACE ....................................................................301
14
15
ABSOLUTE MAXIMUM RATINGS........................................................303
D.C. CHARACTERISTICS....................................................................304
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iv
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