RELEASED
DATA SHEET
PMC-1980582
ISSUE 5
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
PM7351
VORTEX
S
/UNI
-
TM
S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
DATA SHEET
RELEASED
ISSUE 5: MARCH 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
RELEASED
DATA SHEET
PMC-1980582
ISSUE 5
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
REVISION HISTORY
Issue No.
Issue 5
Issue Date
March 2000
Details of Change
Changes marked with side bars.
Incorporated errata items and updated data sheet
for Production Release.
Updated A.C. Timing Characteristics
tH
RCLK
and tH
TCLK
.
Updated D.C. Characteristics R
IN
and V
ODM
in.
Issue 4
Issue 3
Issue 2
January
2000
June 1999
April 1999
Changes marked with side bars.
Matches functionality of PM7351 Rev B
Changed the confidentiality notices for the
document’s public release.
Changes in all areas from Issue 1.
Matches functionality of product
PM7351-BI, Rev A
Preliminary Document
Issue 1
May ,1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
RELEASED
DATA SHEET
PMC-1980582
ISSUE 5
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
CONTENTS
1
2
3
4
5
6
7
8
9
FEATURES .............................................................................................. 1
APPLICATIONS ....................................................................................... 3
REFERENCES......................................................................................... 4
APPLICATION EXAMPLES ..................................................................... 5
BLOCK DIAGRAM ................................................................................... 9
DESCRIPTION ...................................................................................... 10
PIN DIAGRAM ....................................................................................... 12
PIN DESCRIPTION................................................................................ 13
FUNCTIONAL DESCRIPTION............................................................... 29
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
10
11
CELL INTERFACE ...................................................................... 29
HIGH-SPEED SERIAL INTERFACES ......................................... 34
CELL BUFFERING AND FLOW CONTROL ............................... 43
TIMING REFERENCE INSERTION AND RECOVERY ............... 46
JTAG TEST ACCESS PORT....................................................... 47
MICROPROCESSOR INTERFACE ............................................ 47
INTERNAL REGISTERS ............................................................. 51
REGISTER MEMORY MAP ........................................................ 51
NORMAL MODE REGISTER DESCRIPTION ....................................... 55
TEST FEATURES DESCRIPTION .......................................................117
11.1
11.2
RAM BUILT-IN-SELF-TEST ...................................................... 120
JTAG TEST PORT .................................................................... 122
12
OPERATION ........................................................................................ 127
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
i
RELEASED
DATA SHEET
PMC-1980582
ISSUE 5
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
12.1
12.2
12.3
12.4
12.5
13
14
15
16
17
18
19
DETERMINING THE VALUE FOR FREADY[5:0]...................... 127
INTERACTION BETWEEN BUS AND LVDS CONFIGURATIONS
.................................................................................................. 130
MINIMUM PROGRAMMING ..................................................... 134
JTAG SUPPORT ....................................................................... 135
MICROPROCESSOR INBAND COMMUNICATION ................. 141
FUNCTIONAL TIMING......................................................................... 144
ABSOLUTE MAXIMUM RATINGS ....................................................... 147
D.C. CHARACTERISTICS ................................................................... 148
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..... 152
A.C. TIMING CHARACTERISTICS...................................................... 156
ORDERING AND THERMAL INFORMATION...................................... 162
MECHANICAL INFORMATION............................................................ 163
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
RELEASED
DATA SHEET
PMC-1980582
ISSUE 5
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
LIST OF REGISTERS
REGISTER 0X000: MASTER RESET AND IDENTITY / LOAD PERFORMANCE
METERS ................................................................................................ 56
REGISTER 0X001: MASTER CONFIGURATION ............................................ 57
REGISTER 0X002: RECEIVE SERIAL INTERRUPT STATUS......................... 59
REGISTER 0X003: TRANSMIT SERIAL INTERRUPT STATUS ...................... 60
REGISTER 0X004: MISCELLANEOUS INTERRUPT STATUSES................... 61
REGISTER 0X005: CONTROL CHANNEL BASE ADDRESS .......................... 63
REGISTER 0X006: CONTROL CHANNEL BASE ADDRESS MSB ................. 64
REGISTER 0X007: CLOCK MONITOR............................................................ 65
REGISTER 0X008: DOWNSTREAM CELL INTERFACE CONFIGURATION .. 67
REGISTER 0X00A: DOWNSTREAM CELL INTERFACE INTERRUPT ENABLE
............................................................................................................... 69
REGISTER 0X00B: DOWNSTREAM CELL INTERFACE INTERRUPT STATUS
............................................................................................................... 70
REGISTER 0X00C: UPSTREAM CELL INTERFACE CONFIGURATION AND
INTERRUPT STATUS............................................................................ 71
REGISTER 0X010: MICROPROCESSOR CELL BUFFER INTERRUPT
CONTROL AND STATUS....................................................................... 73
REGISTER 0X011: MICROPROCESSOR INSERT FIFO CONTROL.............. 75
REGISTER 0X012: MICROPROCESSOR EXTRACT FIFO CONTROL .......... 77
REGISTER 0X013: MICROPROCESSOR INSERT FIFO READY................... 79
REGISTER 0X014: MICROPROCESSOR EXTRACT FIFO READY ............... 80
REGISTER 0X015: INSERT CRC-32 ACCUMULATOR (LSB)......................... 81
REGISTER 0X016: INSERT CRC-32 ACCUMULATOR (2ND BYTE) .............. 81
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iii
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