• Available in lead-free 44-Lead (400-Mil) Molded SOJ and
44-Pin TSOP II packages
Functional Description
[1]
The CY7C1041D is a high-performance CMOS static RAM
organized as 256K words by 16 bits. Writing to the device is
accomplished by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
), is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041D is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configurations
SOJ / TSOPII
Top View
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
0
–I/O
7
I/O
8
–I/O
15
256K x 16
COLUMN
DECODER
BHE
WE
CE
OE
BLE
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
17
A
16
A
15
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
14
A
13
A
12
A
11
A
10
ROW DECODER
Note:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 38-05472 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 31, 2006
[+] Feedb
CY7C1041D
Selection Guide
-10 (Industrial)
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
10
90
10
-12 (Automotive)
[2]
12
95
15
Unit
ns
mA
mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[3]
.... –0.5V to +6.0V
DC Voltage Applied to Outputs
in High Z State
[3]
.....................................–0.5V to V
CC
+0.5V
DC Input Voltage
[3]
..................................–0.5V to V
CC
+0.5V
Current into Outputs (LOW)......................................... 20 mA
Latch-up Current...................................................... >200 mA
Operating Range
Range
Industrial
Automotive
Ambient
Temperature
–40°C to +85°C
–40°C to +125°C
V
CC
5V
±
0.5
5V
±
0.5
Speed
10 ns
12 ns
Electrical Characteristics
Over the Operating Range
-10 (Industrial)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW
Voltage
[3]
GND < V
OUT
< V
CC
, Output
Disabled
100 MHz
83 MHz
66 MHz
40 MHz
I
SB1
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V, or V
IN
< 0.3V,
f=0
Input Leakage Current GND < V
I
< V
CC
Output Leakage
Current
2.0
–0.5
–1
–1
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
90
80
70
60
20
2.0
–0.5
–1
–1
Max.
-12 (Automotive)
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
-
95
85
75
25
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
V
CC
Operating Supply V
CC
= Max.,
Current
f = f
MAX
= 1/t
RC
I
SB2
10
15
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Notes:
2. Automotive product information is Preliminary.
3. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05472 Rev. *C
Page 2 of 9
[+] Feedb
CY7C1041D
Thermal Resistance
[4]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
[4]
Thermal Resistance
(Junction to Case)
[4]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
SOJ Package TSOP II Package
57.91
36.73
50.66
17.17
Unit
°C/W
°C/W
AC Test Loads and Waveforms
[5]
10 ns device
Z = 50Ω
3.0V
50
Ω
OUTPUT
ALL INPUT PULSES
90%
10%
(b)
90%
10%
≤
3 ns
30 pF*
GND
≤
3 ns
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(a)
High-Z Characteristics:
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
(c)
R1 481
Ω
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Switching Characteristics
[6]
Over the Operating Range
-10 (Industrial)
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
V
CC
(typical) to the First Access
[7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[8, 9]
CE LOW to Low Z
[9]
CE HIGH to High Z
[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
0
5
0
10
5
0
6
3
5
0
12
6
0
5
3
6
3
10
5
0
6
100
10
10
3
12
6
100
12
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
-12 (Automotive)
Min.
Max.
Unit
Notes:
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c)
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
8. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, t
HZBE
is less than t
LZBE,
and t
HZWE
is less than t
LZWE
for any given device.
Document #: 38-05472 Rev. *C
Page 3 of 9
[+] Feedb
CY7C1041D
Switching Characteristics
[6]
Over the Operating Range(continued)
-10 (Industrial)
Parameter
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[9]
WE LOW to High Z
[8, 9]
Byte Enable to End of Write
7
10
7
7
0
0
7
6
0
3
5
10
12
10
10
0
0
10
7
0
3
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
-12 (Automotive)
Min.
Max.
Unit
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
I
CCDR
t
CDR[4]
t
R[12]
Description
V
CC
for Data Retention
Data Retention Current
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
Ind’l
Auto
0
t
RC
Conditions
[13]
Min.
2.0
10
15
Max.
Unit
V
mA
mA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
4.5V
t
CDR
V
DR
> 2V
4.5V
t
R
Switching Waveforms
Read Cycle No. 1
[13, 14]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Notes:
10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the
Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
12. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
µs
or stable at V
CC(min.)
> 50
µs
13. No input may exceed V
CC
+ 0.5V
14. Device is continuously selected. OE, CE, BHE, and/or BHE = V
IL
.
Document #: 38-05472 Rev. *C
Page 4 of 9
[+] Feedb
CY7C1041D
Switching Waveforms
(continued)
Read Cycle No. 2 (OE Controlled)
[15,16]
ADDRESS
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
50%
DATA VALID
t
PD
50%
ISB
t
HZCE
t
HZBE
t
HZOE
HIGH
IMPEDANCE
ICC
Write Cycle No. 1 (CE Controlled)
[17, 18]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
PWE
WE
t
BW
BHE, BLE
t
SD
DATAI/O
t
HD
t
HA
Notes:
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW
17. Data I/O is high impedance if OE or BHE and/or BLE= V
IH
.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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