W29F102P-45B datasheet, PDF - EEWORLD Datasheet

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W29F102P-45B: Description64k 16 cmos flash memory; Categorystorage storage; File Size200KB，21 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W29F102P-45B Overview

64k 16 cmos flash memory

W29F102P-45B Parametric

Parameter Name	Attribute value
Maker	Winbond Electronics Corporation
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	44
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	45 ns
Other features	HARDWARE DATA PROTECTION; 10 YEARS DATA RETENTION
Data retention time - minimum	10
JESD-30 code	S-PQCC-J44
length	16.5862 mm
memory density	1048576 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of terminals	44
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX16
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	4.7 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
type	NOR TYPE
width	16.5862 mm

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W29F102

64K

16 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29F102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K

16 bits. The

device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V

not required. The unique cell architecture of the W29F102 results in fast program/erase operations

with extremely low current consumption (compared to other comparable 5-volt flash memory

products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

•

Single 5-volt operations:

−

5-volt Read

−

5-volt Erase

−

5-volt Program

•

Low power consumption

−

Active current: 25 mA (typ.)

−

Standby current: 20

µA

(typ.)

•

Fast Program operation:

−

Word-by-Word programming: 50

µS

(max.)

Fast Erase operation: 100 mS (typ.)

Fast Read access time: 45/50/55/70 nS

Endurance: 1K/10K cycles (typ.)

Ten-year data retention

Hardware data protection

8K word Boot Block with Lockout protection

•

Automatic program and erase timing with

internal V

generation

End of program or erase detection

−

Toggle bit

−

Data polling

Latched address and data

TTL compatible I/O

JEDEC standard word-wide pinouts

Available packages: 40-pin TSOP and 44-pin

PLCC

•

-1-

Publication Release Date: June 1999

Revision A4

W29F102

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29F102 is controlled by CE and OE, both of which have to be low for

the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip

is de-selected and only standby power will be consumed. OE is the output control and is used to gate

data from the output pins. The data bus is in high impedance state when either CE or OE is high.

Refer to the timing waveforms for further details.

Boot Block Operation

There is one 8K-word boot block in this device, which can be used to store boot code. It is located in

the first 8K words of the memory with the address range from 0000 hex to 1FFF hex.

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set

the data for the designated block cannot be erased or programmed (programming lockout); other

memory locations can be changed by the regular programming method. Once the boot block

programming lockout feature is activated, the chip erase function will only affect the main memory.

In order to detect whether the boot block feature is set on the 8K-words block, users can perform

software command sequence: enter the product identification mode (see Command Codes for

Identification/Boot Block Lockout Detection for specific code), and then read from address "0002

hex". If the output data is "FF hex," the boot block programming lockout feature is activated; if the

output data is "FE hex," the lockout feature is inactivated and the block can be erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word

command) to exit the identification mode. For the specific code, see Command Codes for

Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading

cycle, the device enters the internal chip erase mode, which is automatically timed and will be

completed in a fast 100 mS (typical). The host system is not required to provide any control or timing

during this operation. If the boot block programming lockout is activated, only the data in the main

memory will be erased to FF(hex), and the data in the boot block will not be erased (remains same as

before the chip erase operation). The entire memory array (main memory and boot block) will be

erased to FF hex. by the chip erase operation if the boot block programming lockout feature is not

activated. The device will automatically return to normal read mode after the erase operation

completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

Main Memory Erase Operation

The main memory erase mode can be initiated by a six-word command sequence. After the

command loading cycle, the device enters the internal main-memory erase mode, which is

automatically timed and will be completed in a fast 100 mS (typical). The host system is not required

to provide any control or timing during this operation. The device will automatically return to normal

read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect

end of erase cycle.

-3-

Publication Release Date: June 1999

Revision A4

W29F102

Program Operation

The W29F102 is programmed on a word-by-word basis. Program operation can only change logical

data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot

block from "0" to "1" is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Word

Programming). The device will interally enter the program operation immediately after the word-

program command is entered. The internal program timer will automatically time-out (50

µS

max. -

) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to

detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W29F102 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The programming operation is inhibited when V

is less than

2.5V typical.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ

7 &

)- Write Status Detection

The W29F102 includes a data polling feature to indicate the end of a program or erase cycle. When

the W29F102 is in the internal program or erase cycle, any attempt to read DQ

or DQ

of the last

word loaded will receive the complement of the true data. Once the program or erase cycle is

completed, DQ

or DQ

will show the true data. Note that DQ

or DQ

will show logical "0" during

the erase cycle, and become logical "1" or true data when the erase cycle has been completed.

Toggle Bit (DQ

& DQ

)- Write Status Detection

In addition to data polling, the W29F102 provides another method for determining the end of a

program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ

will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling

between 0's and 1's will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment

automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the

software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the

product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address

0001H outputs the device code (002Fh). The product ID operation can be terminated by a three-word

command sequence or an altenate one-word command sequence (see Command Definition table).

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE

high, and raising A9 to 12 volts.

-4-

W29F102P-45B Related Products

	W29F102P-45B	W29F102	W29F102P-45
Description	64k 16 cmos flash memory	64k 16 cmos flash memory	64k 16 cmos flash memory
Maker	Winbond Electronics Corporation	-	Winbond Electronics Corporation
Parts packaging code	LCC	-	LCC
package instruction	QCCJ,	-	QCCJ,
Contacts	44	-	44
Reach Compliance Code	unknow	-	unknow
ECCN code	EAR99	-	EAR99
Maximum access time	45 ns	-	45 ns
Other features	HARDWARE DATA PROTECTION; 10 YEARS DATA RETENTION	-	HARDWARE DATA PROTECTION; 10 YEARS DATA RETENTION
Data retention time - minimum	10	-	10
JESD-30 code	S-PQCC-J44	-	S-PQCC-J44
length	16.5862 mm	-	16.5862 mm
memory density	1048576 bi	-	1048576 bi
Memory IC Type	FLASH	-	FLASH
memory width	16	-	16
Number of functions	1	-	1
Number of terminals	44	-	44
word count	65536 words	-	65536 words
character code	64000	-	64000
Operating mode	ASYNCHRONOUS	-	ASYNCHRONOUS
Maximum operating temperature	70 °C	-	70 °C
organize	64KX16	-	64KX16
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	QCCJ	-	QCCJ
Package shape	SQUARE	-	SQUARE
Package form	CHIP CARRIER	-	CHIP CARRIER
Parallel/Serial	PARALLEL	-	PARALLEL
Programming voltage	5 V	-	5 V
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	4.7 mm	-	4.7 mm
Maximum supply voltage (Vsup)	5.5 V	-	5.5 V
Minimum supply voltage (Vsup)	4.5 V	-	4.5 V
Nominal supply voltage (Vsup)	5 V	-	5 V
surface mount	YES	-	YES
technology	CMOS	-	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL
Terminal form	J BEND	-	J BEND
Terminal pitch	1.27 mm	-	1.27 mm
Terminal location	QUAD	-	QUAD
type	NOR TYPE	-	NOR TYPE
width	16.5862 mm	-	16.5862 mm

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