pLSI3256-70LG datasheet, PDF - EEWORLD Datasheet

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pLSI3256-70LG: DescriptionHigh Density Programmable Logic; CategoryProgrammable logic devices Programmable logic; File Size1MB，18 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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pLSI3256-70LG Overview

High Density Programmable Logic

pLSI3256-70LG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	PGA
package instruction	CERAMIC, PGA-167
Contacts	167
Reach Compliance Code	compli
ECCN code	EAR99
Other features	5 EXTERNAL CLOCKS
maximum clock frequency	50 MHz
In-system programmable	NO
JESD-30 code	S-CPGA-P167
JESD-609 code	e0
JTAG BST	NO
length	44.45 mm
Dedicated input times
Number of I/O lines	128
Number of macro cells	256
Number of terminals	167
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 128 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA167,17X17
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	EE PLD
propagation delay	18 ns
Certification status	Not Qualified
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	44.45 mm

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pLSI3256-70LG Related Products

	pLSI3256-70LG	3256	pLSI3256-50LM	pLSI3256-50LG	ispLSI3256-50LG	ispLSI3256-70LG	ispLSI3256-50LM
Description	High Density Programmable Logic	High Density Programmable Logic	High Density Programmable Logic	High Density Programmable Logic	High Density Programmable Logic	High Density Programmable Logic	High Density Programmable Logic
Is it Rohs certified?	incompatible	-	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Lattice	-	Lattice	Lattice	Lattice	Lattice	Lattice
Parts packaging code	PGA	-	QFP	PGA	PGA	PGA	QFP
package instruction	CERAMIC, PGA-167	-	MQFP-160	CERAMIC, PGA-167	CERAMIC, PGA-167	CERAMIC, PGA-167	MQFP-160
Contacts	167	-	160	167	167	167	160
Reach Compliance Code	compli	-	compliant	compliant	compliant	compli	compliant
ECCN code	EAR99	-	EAR99	EAR99	EAR99	EAR99	EAR99
Other features	5 EXTERNAL CLOCKS	-	5 EXTERNAL CLOCKS	5 EXTERNAL CLOCKS	IN-SYSTEM PROGRAMMABLE; 5 EXTERNAL CLOCKS	IN-SYSTEM PROGRAMMABLE; 5 EXTERNAL CLOCKS	IN-SYSTEM PROGRAMMABLE; 5 EXTERNAL CLOCKS
maximum clock frequency	50 MHz	-	37 MHz	37 MHz	37 MHz	50 MHz	37 MHz
In-system programmable	NO	-	NO	NO	YES	YES	YES
JESD-30 code	S-CPGA-P167	-	S-PQFP-G160	S-CPGA-P167	S-CPGA-P167	S-CPGA-P167	S-PQFP-G160
JESD-609 code	e0	-	e0	e0	e0	e0	-
JTAG BST	NO	-	NO	NO	YES	YES	YES
length	44.45 mm	-	27.69 mm	44.45 mm	44.45 mm	44.45 mm	27.69 mm
Number of I/O lines	128	-	128	128	128	128	128
Number of macro cells	256	-	256	256	256	256	256
Number of terminals	167	-	160	167	167	167	160
Maximum operating temperature	70 °C	-	70 °C	70 °C	70 °C	70 °C	70 °C
organize	0 DEDICATED INPUTS, 128 I/O	-	0 DEDICATED INPUTS, 128 I/O	0 DEDICATED INPUTS, 128 I/O	0 DEDICATED INPUTS, 128 I/O	0 DEDICATED INPUTS, 128 I/O	0 DEDICATED INPUTS, 128 I/O
Output function	MACROCELL	-	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED	-	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY
encapsulated code	PGA	-	QFP	PGA	PGA	PGA	QFP
Encapsulate equivalent code	PGA167,17X17	-	QFP160,1.2SQ	PGA167,17X17	PGA167,17X17	PGA167,17X17	QFP160,1.2SQ
Package shape	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	-	FLATPACK	GRID ARRAY	GRID ARRAY	GRID ARRAY	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	225	225	225
power supply	5 V	-	5 V	5 V	5 V	5 V	5 V
Programmable logic type	EE PLD	-	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	18 ns	-	24.5 ns	24.5 ns	24.5 ns	18 ns	24.5 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	5.25 V	-	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	-	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	-	5 V	5 V	5 V	5 V	5 V
surface mount	NO	-	YES	NO	NO	NO	YES
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	PIN/PEG	-	GULL WING	PIN/PEG	PIN/PEG	PIN/PEG	GULL WING
Terminal pitch	2.54 mm	-	0.65 mm	2.54 mm	2.54 mm	2.54 mm	0.65 mm
Terminal location	PERPENDICULAR	-	QUAD	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	30	30	NOT SPECIFIED
width	44.45 mm	-	27.69 mm	44.45 mm	44.45 mm	44.45 mm	27.69 mm
Base Number Matches	-	-	1	1	1	-	1

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