PLL702-01
Clock Generator for PowerPC Based Applications
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
PIN ASSIGNMENT (28 pin SSOP)
CPUDRV_SEL^
XIN
XOUT / ASIC2_OE*^
VDD_ANA
VDD_DIG
VDD_PC I
PCI / PCI_SEL*
T
GND_PCI
GND_USB
VDD_USB
USB / USB_SEL*
T
VDD_ASIC2
ASIC2 A
ASIC2 B
Note :
1 CPU Clock output with selectable frequencies (50,
66, 75, 80, 83, 90, 100,125 or 133 MHz).
1 ASIC output clock (at CPU clock or CPU clock ÷ 2).
2 ASIC output clocks (at CPU clock) w/ output enable.
1 PCI output clock w/ output enable
1 Selectable 48, 30 or 12MHz (USB) output.
Selectable Spread Spectrum (SST) for EMI reduction
on ASIC and CPU.
PowerPC compatible output and drive CPU Clock.
Selectable reduced 67% drive strength on CPU Clock
Advanced, low power, sub-micron CMOS processes.
14.31818MHz fundamental crystal input.
3.3V and/or 2.5V operation.
Available in 28-Pin 209mil SSOP (QSOP)
.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK_SEL0
T
CLK_SEL1
T
SSCO
^
SSC1
^
GND_ANA
GND_CPU
CP U
o
VDD_CPU
VDD_ASIC1
ASIC1
GND_ASIC1
^
ASIC1_SEL
GND_DIG
GND_ASIC2
o
:
^: Internal pull-up resistor
Selectable reduced drive
strength
DESCRIPTION
The PLL702-01 is a low cost, low jitter, and high
performance clock synthesizer for generic PowerPC based
applications. It provides one CPU clock, three ASIC
outputs, one PCI output, and a selectable 48, 30 or 12MHz
(USB) output. The user can choose between 9 different
CPU clock frequencies, while the ASIC output can be
identical or half of the CPU frequency. Low EMI Spread
Spectrum Technology is available for the CPU, ASIC and
PCI clocks. The CPU drive strength is user selectable from
100% to 67%. All frequencies are generated from a single
low cost 14.31818MHz crystal. The CPU and ASIC clock
can be driven from an independent 2.5V power supply.
FREQUENCY TABLES
CLK_SEL1
CLK_SEL0
CPU
(MHz)
ASIC1 (MHz)
ASIC1_SEL
=1
ASIC1_SEL
=0
PLL702-01
*: Bi-directional pin
T
Tri-level input
:
ASIC2
(MHz)
PCI* (MHz)
PCI_SEL
=0
PCI_SEL
=M
0
0
0
M
M
M
1
1
1
Notes:
0
M
1
0
M
1
0
M
1
50
66
75
80
83
90
100
125
133
50
66
75
80
83
90
100
125
133
25
33
37.5
40
41.5
45
50
62.5
66.5
50
66
75
80
83
90
100
125
133
62.5
66.7
62.5
66.7
66.7
66.7
66.7
62.5
65.5
31.25
33.35
31.25
33.35
33.35
33.35
33.35
31.25
32.75
When CPU=90MHz, it implements 88.88MHz to meet PCI=33.3MHz/66.6MHz; When
CPU=133MHz, it implements 130.9MHz to meet Power PC clock AC Timing Specification.
* PCI_SEL=1 sets the Tri-state (output disabled) mode of the output.
BLOCK DIAGRAM
USB_SEL
Control
Logic
PLL
USB
CPU_CLK
PLL
SST
DIV 2
ASIC2_OE
PCI
PCI_OE
Control
Logic
ASIC1
ASIC2(A:B)
XIN
XOUT
SSC(0:1)
CLK_SEL(0:1)
ASIC1_SEL
PCI_SEL
XTAL
OSC
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 1
PLL702-01
Clock Generator for PowerPC Based Applications
PIN DESCRIPTIONS
Name
CPUDRV_SEL
Number
1
Type
I
Description
CPU drive strength selector pin. The CPU drive strength can be set to 67% of
nominal strength with CPUDRV_SEL = 0. When CPUDRV_SEL = 1, the CPU
drive strength will be 100% of the nominal strength. Internal pull-up of 60kΩ.
0=connect to GND, 1=leave open.
Crystal input to be connected to a 14.31818MHz fundamental crystal (CL =
20pF, parallel resonant mode). Load capacitors have been integrated on the
chip. No external Load capacitor is required.
Bi-directional pin. Upon power-on, the value of ASIC2_OE is latched in and
used to enable / disable the ASIC2A and ASIC2B outputs (outputs are
enabled if ASIC2_OE=1, otherwise, outputs are in tri-state). Internal pull-up of
120 kΩ. After the input has been latched-in, the pin serves as Crystal
connection.
3.3V power supply and GND.
CPU, PCI, ASIC1 and ASIC2 outputs have separate power supply pins (VDD
and GND). VDD_CPU, VDD_ASIC1 and VDD_ASIC2 can accept 3.3V and/or
2.5V power supply. Other VDD pins are to be supplied 3.3V
Bi-directional pin. Upon power-on, the value of PCI_SEL is latched in and
used to select the PCI clock output (see frequency table on p.1). PCI output is
disabled (tri-state) when PCI_SEL=1. PCI clock will be 33MHz (min.
31.25MHz) if PCI_SEL=M (not connected), and 66MHz (min. 62.5MHz) if
PCI_SEL=0. 0=15kΩ to GND, M=leave open, 1=15kΩ to VDD_PCI
Bi-directional pin. Upon power-on, the value of USB_SEL is latched in and
used to select the USB output (see USB selection table on page 3). After the
input has been latched-in, the pin serves as USB (48, 30 or 12 MHz) output.
0=15kΩ to GND, M=leave open, 1=15kΩ to VDD_USB
ASIC clock signal output pins. ASIC2A and ASIC2B will have the same
frequency as CPU. These outputs can be disabled through ASIC2_OE.
ASIC1 frequency select input pin (see also frequency table on p.1). ASIC1 will
have the same frequency as CPU if ASIC1_SEL = 1, and have half of CPU if
ASIC_SEL = 0. Internal pull-up of 60 kΩ. 0=connect to GND, 1=leave open
ASIC1 output pin (see frequency table on p.1 and ASIC1_SEL pin
description).
CPU clock signal output pin. The CPU clock frequency is selected as per the
frequency table on page 1, depending on the value of CLK_SEL(0:1).
Selectable drive strength through CPUDRV_SEL.
Bi-level input with Pull-up for SST control (see Spread Spectrum selection
table on p.3). 0=connect to GND, 1=leave open.
Tri-level inputs for CPU clock frequency selection (see table on p.1).
0=connect to GND, M=not connected, 1=connect to VDD_ANA.
XIN
2
I
XOUT/ ASIC2_OE
VDD_ANA / GND_ANA
VDD_DIG / GND_DIG
VDD_xxx / GND_xxx
for USB, CPU, PCI,
ASIC1 and ASIC2
3
4, 5, 16,
24
6, 8, 9,
10, 12,
15, 18,
20, 21, 23
7
B
P
P
PCI / PCI_SEL
B
USB /
USB_SEL
ASIC2A and ASIC2B
ASIC1_SEL
ASIC1
CPU
SSC(0:1)
CLK_SEL(0:1)
11
13, 14
17
19
22
25, 26
27, 28
B
O
I
O
O
I
I
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 2
PLL702-01
Clock Generator for PowerPC Based Applications
USB OUTPUT FREQUENCY AND CPU DRIVE STRENGTH SELECTION TABLES
USB_SEL
0
M
1
USB
48 MHz
30 MHz
12 MHz
CPUDRV_SEL
0
1
CPU drive strength
67% (reduced)
100% (nominal)
SPREAD SPECTRUM SELECTION TABLE
SSC1
0
0
1
1
SSC0
0
1
0
1
Spread Spectrum Modulation
OFF
- 0.50% – Downspread
- 1.00% – Downspread
- 1.25% – Downspread
FUNCTIONAL DESCRIPTION
Tri-level and two-level inputs
In order to reduce pin usage, the PLL702-01 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 =
Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are
in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to
GND. Likewise, in order to connect to a logical “one”, the pin must be connected to VDD.
Connecting a bi-directional pin
The PLL702-01 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs
have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can
be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in
order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-
up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin
and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-
directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up
resistor.
Note:
when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up
resistor may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.
For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the
internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the
pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is
recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application
Diagram).
Note:
when the output is used to drive a load presenting an small resistance between the output pin and VDD, this
resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may
have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is
particularly true when driving 74FXX TTL components.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 3
PLL702-01
Clock Generator for PowerPC Based Applications
APPLICATION DIAGRAM: BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP
Internal to chip
VDD
External Circuitry
R
up
Power Up
Reset
R
RB
Output
EN
Bi-directional pin
Clock Load
Latched
Input
Latch
R
UP
/
4
Jumper options
NOTE:
Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 4
PLL702-01
Clock Generator for PowerPC Based Applications
VDD Power Up Ramp requirements:
At startup, the chip reads a lot of settings for operation according to the application’s requirements. Since reading the settings is
done only at startup and then frozen for the time of operation, it is important that the power-up environment is somewhat
controlled to facilitate proper reading of the settings. The important VDD pins are VDD_ANA and VDD_DIG and they should
apply to the following two-startup requirements:
1. VDD_DIG should be equally fast or slower than VDD_ANA. VDD_DIG performs a chip reset when VDD has reached a
certain level and VDD_ANA should have reached at least up to the same level as well to properly process the reset.
2. The VDD Power Up Ramp of VDD_DIG and VDD_ANA should pass through the section 1.8V to 2.5V no faster than 100µs
and with a continuously increasing slope. In this section the tri-level select inputs are read.
3. After VDD Power off, VDD should be allowed to go to 0V and stay there for at least 1ms before a new VDD Power on. It is
important that proper preconditions exist at every startup. Remaining charges in the chip or in circuit filter capacitors may
interfere with the preconditions so it is important that VDD has been at 0V for some time before each startup.
VDD off
3.3V
2.97V
2.5V
2.2V
1.8V
VDD on
GND (0V)
No limit
Reset enable
Min 1ms
>100us
Min 1s
Reset disable
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 5
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