PLL620-28/-29
Low Phase Noise VCXO (for 100-200MHz Fund Xtal)
FEATURES
•
•
•
•
•
•
•
100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100 – 200MHz (no PLL).
Low Injection Power for crystal 50uW.
Sub 0.5pS RMS phase jitter ( 12kHz to 20MHz ).
PECL (PLL620-28) or LVDS output (PLL620-29).
Supports 2.5V or 3.3V-Power Supply.
Available in 16-Pin TSSOP.
PIN CONFIGURATION
(Top View)
DESCRIPTION
The PLL620-28/-29 family of XO ICs is specifically
designed to work with high frequency fundamental
and third overtone crystals. They achieve very low
current into the crystal, resulting in better stability.
Their very low jitter makes them ideal for the most
demanding timing requirements.
BLOCK DIAGRAM
OE
Q
XIN
XOUT
Oscillator
Amplifier
Q
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL620-28
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
PLL620-28/-29
PLL620-29
OE input: Logical states defined by PECL levels for PLL620-28
Logical states defined by CMOS levels for PLL620-29
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/08/05 Page 1
PLL620-28/-29
Low Phase Noise VCXO (for 100-200MHz Fund Xtal)
PIN DESCRIPTIONS
Name
XIN
XOUT
OE
GND
CLKT
CLKC
DNC
VDD
Pin number
2
3
6
8, 9, 10, 14
11
13
4, 5, 7, 15, 16
1, 12
Type
I
I
I
P
O
O
-
P
Description
Crystal input. See Crystal Specifications on page 2.
Crystal output. See Crystal Specifications on page 2.
Output enable pin. See Output Enable Logic Levels on page 1.
Ground.
True output PECL (PLL620-28) or LVDS (PLL620-29)
Complementary output PECL (PLL620-28) or LVDS (PLL620-29).
DO Not connect.
Power supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Built-in Load Capacitance
Shunt Capacitance
Oscillation Frequency
Recommended ESR
SYMBOL
C
L
C
0
OF
R
E
CONDITIONS
IC only, no PCB
capacitance included.
Fund. Or 3
rd
Overtone
MIN.
TYP.
4
MAX.
UNITS
pF
100
2
200
30
pF
MHz
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/08/05 Page 2
PLL620-28/-29
Low Phase Noise VCXO (for 100-200MHz Fund Xtal)
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
MIN.
TYP.
MAX.
100/80
UNITS
mA
V
%
mA
2.97
45
45
50
50
±50
3.63
55
55
4. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-peak
Integrated jitter RMS at 155MHz
CONDITIONS
At 155.52MHz, with capacitive decoupling
between VDD and GND.
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000
cycles.
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5
18.5
2.5
24
0.3
MAX.
UNITS
ps
ps
ps
5. Phase Noise Specifications
PARAMETERS
Phase Noise relative to carrier
FREQUENCY
155.52MHz
@10Hz
-80
@100Hz
-110
@1kHz
-125
@10kHz
-143
@100kHz
-145
UNITS
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/08/05 Page 3
PLL620-28/-29
Low Phase Noise VCXO (for 100-200MHz Fund Xtal)
6. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
V
out
= V
DD
or GND
V
DD
= 0V
7. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
C
L
= 10pF
50Ω
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/08/05 Page 4
PLL620-28/-29
Low Phase Noise VCXO (for 100-200MHz Fund Xtal)
8. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
V
OH
V
OL
CONDITIONS
R
L
= 50
Ω
to (V
DD
– 2V)
(see figure)
MIN.
V
DD
– 1.025
MAX.
V
DD
– 1.620
UNITS
V
V
9. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
t
r
t
f
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
TYP.
0.6
0.5
MAX.
1.5
1.5
UNITS
ns
ns
PECL Levels Test Circuit
OUT
VDD
OUT
PECL Output Skew
50Ω
2.0V
50%
50Ω
OUT
OUT
t
SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/08/05 Page 5
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