Preliminary
PLL520-88/-89
Low Phase Noise VCXO (9.5-65MHz)
FEATURES
•
•
•
•
•
•
•
19MHz to 65MHz fundamental crystal input.
Output range: 9.5MHz – 65MHz
Complementary outputs: PECL or LVDS output.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 2.5V or 3.3V Power Supply.
Available in 16 pin TSSOP package.
PIN CONFIGURATION
VDD
XIN
XOUT
DNC
S2
OE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DNC
DNC
GNDBUF
QBAR
VDDBUF
Q
GNDBUF
GND
PLL 520-8x
DESCRIPTION
The PLL520-88 (PECL) and PLL520-89 (LVDS) are
VCXO ICs specifically designed to work with
fundamental crystals between 19MHz and 65MHz.
The selectable divide by two feature extends the
operation range from 9.5MHz to 65MHz. They
require very low current into the crystal resulting in
better overall stability. The OE logic feature allows
selection of enable high or enable low.
VCON
GND
OUTPUT SELECTION AND ENABLE
OE_SELECT
OE_CTRL
State
0
BLOCK DIAGRAM
1 (Default)
0
1 (Default)
0 (Default)
1
Tri-state
Output enabled
Output enabled
Tri-state
O
Q
VCON
X+
X-
Oscillator
Amplifier
with
Integrated
Varicaps
Q
S2
Input selection: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through
internal pull-up/-down.
OE_CTRL:
Logical states defined by PECL levels if
OE_SELECT is “1”
Logical states defined by CMOS levels if
OE_SELECT is “0”
OUTPUT FREQUENCY DIVIDE BY
TWO SELECTOR
S2
Output
PLL520-8X Block Diagram
0
1
Intput/2
Input
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 1
Preliminary
PLL520-88/-89
Low Phase Noise VCXO (9.5-65MHz)
PIN AND PAD ASSIGNMENT
Name
VDD
XIN
XOUT
DNC
S2
OE_CTRL
VCON
GND
GNDBUF
Q
VDDBUF
QBAR
GNDBUF
DNC
DNC
Pin#
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
Description
Power Supply.
Crystal input. See Crystal Specification on page 3.
Crystal output. See Crystal Specification on page 3.
Do Not Connect.
Output Divide by Two selector pin. See the OUTPUT DIVIDE BY TWO SELECTOR Table on
page 1.
Output Enable input. See OUTPUT SELECTION AND ENABLE TABLE on page 1.
Voltage control input.
Ground.
Ground for output buffer circuitry.
PECL or LVDS output.
Power supply for output buffer circuitry.
Complementary PECL or LVDS output.
Ground for output buffer circuitry.
Do Not Connect.
Do Not Connect.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 2
Preliminary
PLL520-88/-89
Low Phase Noise VCXO (9.5-65MHz)
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Interelectrode Capacitance
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
R
E
CONDITIONS
Fundamental
Die
AT cut
MIN.
19
TYP.
8*
MAX.
65
5
30
UNITS
MHz
pF
pF
Ω
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific
limits.
3. Voltage Control Crystal Oscillator (3.3V)
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
On-chip Varicaps control range
Linearity
VCXO Tuning Characteristic
VCON input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 19 – 65MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
VCON = 0 to 3.3V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
pF
%
ppm/V
kΩ
kHz
200*
±100*
4 – 18*
10*
65
60
0V
≤
VCON
≤
3.3V, -3dB
25
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific
limits.
4. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
MIN.
TYP.
MAX.
100/80
UNITS
mA
V
%
mA
2.97
45
45
45
50
50
50
±50
3.63
55
55
55
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 3
Preliminary
PLL520-88/-89
Low Phase Noise VCXO (9.5-65MHz)
5. Jitter Specifications
PARAMETERS
Period jitter RMS at 27MHz
Period jitter peak-to-peak at 27MHz
Accumulated jitter RMS at 27MHz
Accumulated jitter peak-to-peak at
27MHz
Random Jitter
Measured on Wavecrest SIA 3000
CONDITIONS
With capacitive decoupling
between VDD and GND. Over
10,000 cycles
With capacitive decoupling
between VDD and GND. Over
1,000,000 cycles.
“RJ” measured on Wavecrest SIA
3000
MIN.
TYP.
2.3
18.5
2.3
24
2.3
MAX.
20
UNITS
ps
25
ps
ps
6. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
27MHz
@10Hz
-75
@100Hz
-100
@1kHz
-125
@10kHz
-140
@100kHz
-145
UNITS
dBc/Hz
Note: Phase Noise measured on Agilent E5500
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 4
Preliminary
PLL520-88/-89
Low Phase Noise VCXO (9.5-65MHz)
7. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
MAX.
454
50
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
1.4
0.9
1.125
0
1.1
1.2
3
±1
-5.7
1.6
1.375
25
±10
-8
V
out
= V
DD
or GND
V
DD
= 0V
8. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 5
Embedded System
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