PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
FEATURES
•
•
•
•
•
•
•
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 800MHz (selectable 1x,
2x, 4x and 8x multipliers).
Low Injection Power for crystal 50uW.
Available outputs: PECL, LVDS, or CMOS.
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in 16 pin (TSSOP or SOIC)
PIN CONFIGURATION
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
PLL 520-1x
DESCRIPTION
The PLL520-17/-18/-19 family of VCXO IC’s is
specifically designed to pull high frequency
fundamental crystals. They achieve very low current
into the crystal resulting in better overall stability.
Their internal varicaps allow an on chip frequency
pulling, controlled by the VCON input.
^: Internal pull-up
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL520-18
PLL520-17
PLL520-19
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
BLOCK DIAGRAM
OE input: Logical states defined by PECL levels for PLL520-18
Logical states defined by CMOS levels for PLL520-17/-19
SEL
OE
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
Q
Q
PLL by-pass
PLL520-17/-18/-19
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 1
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
PIN DESCRIPTIONS
Name
XIN
XOUT
OE
VCON
GND
CLKT
CLKC
SEL
VDD
Number
2
3
6
7
8,9, 10, 14
11
13
4,5,15,16
1, 12
Type
I
I
I
I
P
O
O
I
P
Description
Crystal input. See Crystal Specification on page 3.
Crystal output. See Crystal Specification on page 3.
Output enable. See Output Enable Logic Levels on page 1.
Voltage control input.
Ground.
True output PECL (PLL520-18) or LVDS (PLL520-19).
No Connect for CMOS (PLL520-17).
Complementary output PECL (PLL520-18) or LVDS (PLL520-19).
CMOS output for (PLL520-17).
Multiplier selector pins. These pins have an internal pull-up that will
default SEL to ‘1’ when not connected to GND.
+3.3V power supply.
FREQUENCY SELECTION TABLE
Pin #4
SEL3
Pin #5
SEL2
Pin #15
SEL1
Pin #16
SEL0
Selected Multiplier
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
Fin x 8
Fin x 4
Fin x 2
No multiplication
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 2
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
2. Crystal Specifications
PARAMETERS
Built-in Capacitance
Inter-electrode capacitance
C0/C1 ratio (gamma)
Oscillation Frequency
SYMBOL
CX+
CX-
C
0
γ
OF
CONDITIONS
65MHz to 130MHz
(VDD=3.3V)
MIN.
MAX.
2
2
2
300
200
UNITS
pF
-
MHz
Fund.
120
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
On-chip Varicaps control range
Linearity
VCXO Tuning Characteristic
VCON input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 100 – 200MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
VCON = 0 to 3.3V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
pF
%
ppm/V
kΩ
kHz
200*
±100*
4 – 18*
10*
65
60
0V
≤
VCON
≤
3.3V, -3dB
25
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS/CMOS
@ 1.4V (CMOS)
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
MIN.
TYP.
MAX.
100/80/40
UNITS
mA
V
%
mA
2.97
45
45
45
50
50
50
±50
3.63
55
55
55
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 3
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
5. Jitter Specifications
PARAMETERS
Period jitter RMS
CONDITIONS
77.76MHz
155.52MHz
622.08MHz
77.76MHz
155.52MHz
622.08MHz
Integrated 12 kHz to 20 MHz at 77.76MHz
Integrated 12 kHz to 20 MHz at 155.52MHz
Integrated 12 kHz to 20 MHz at 622.08MHz
MIN.
TYP.
2.5
4
5
24
29
32
0.5
1.5
1.5
MAX.
UNITS
ps
Period jitter peak-to-peak
ps
Integrated jitter RMS
ps
6. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
77.76MHz
155.52MHz
622.08MHz
@10Hz
-75
-75
-75
@100Hz
-95
-95
-95
@1kHz
-125
-120
-115
@10kHz
-145
-125
-118
@100kHz
-155
-123
-115
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
7. CMOS Output Electrical Specifications
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
I
OH
I
OL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
MIN.
30
30
10
10
TYP.
MAX.
UNITS
mA
mA
mA
mA
2.4
1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 4
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
8. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
V
out
= V
DD
or GND
V
DD
= 0V
9. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 5
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