chips. They provide phase noise performance as low
as –125dBc at 10kHz offset (at 155MHz), by multi-
plying the input crystal frequency up to 32x. The
wide pull range (+/- 200 ppm) and very low jitter
make them ideal for a wide range of applications,
including SONET/SDH and FEC. They accept fun-
damental parallel resonant mode crystals from 12 to
25MHz.
XOUT
SEL3^
SEL2^
OE
13
14
15
16
12
11
10
SEL1^
9
DESCRIPTION
XIN
SEL0^ / VDD*
VDD / GND*
P502-3x
1
2
3
4
PLL 502-3x
GND
GND
8
7
6
5
GND
CLKC
VDD
CLKT
VCON
BLOCK DIAGRAM
SEL
OE
Vin
X+
X-
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
^:
*:
Internal pull-up
On 3x3 package, PLL502-35/-38 do not have SEL0 available: Pin
10 is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0
(pin 10), and pin11 is VDD. See pin assignment table for details.
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL502-38
PLL502-35
PLL502-37
PLL502-39
OE
0 (Default)
1
0
1 (Default)
Tri-state
Tri-state
GND
State
Output enabled
Q
Q
Output enabled
PLL by-pass
PLL502-3x
OE input: Logical states defined by PECL levels for PLL502-38
Logical states defined by CMOS levels for PLL502-37/-39
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/19/06 Page 1
PLL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FREQUENCY SELECTION TABLE
SEL3
0
0
0
1
1
1
1
1
1
1
SEL2
0
1
1
0
0
0
1
1
1
1
SEL1
1
1
1
0
1
1
0
0
1
1
SEL0
1
0
1
1
0
1
0
1
0
1
Selected Multiplier
Fin x 32
Fin / 8
Fin x 2
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
Note:
SEL0 is not available (always “1”) for PLL502-35 and PLL502-38 in 3x3mm package
PIN DESCRIPTIONS PLL502-35 and PLL502-38 (see next page of PLL502-37/-39)
Name
XIN
XOUT
OE
VCON
GND
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
VDD
TSSOP
Pin number
2
3
6
7
8,9,10,14
11
13
16
15
5
4
1, 12
3x3mm QFN
Pin number
12
13
16
1
2,3,4,8,11
5
7
Not available
9
15
14
6,10
Type
I
I
I
I
P
O
O
I
I
I
I
P
Description
Crystal input. See Crystal Specification on page 4.
Crystal output. See Crystal Specification on page 4.
Output enable pin (see OE logic state table on page 1).
Voltage Control input.
Ground.
True output PECL
Complementary output PECL.
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
+3.3V power supply.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/19/06 Page 2
PLL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
PIN DESCRIPTIONS PLL502-37/-39 (see previous page of PLL502-35/-38)
Name
XIN
XOUT
OE
VCON
GND
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
VDD
TSSOP
Pin number
2
3
6
7
8,9,10,14
11
13
16
15
5
4
1, 12
3x3mm QFN
Pin number
12
13
16
1
2,3,4,8
5
7
10
9
15
14
6,11
Type
I
I
I
I
P
O
O
I
I
I
I
P
Description
Crystal input. See Crystal Specification on page 4.
Crystal output. See Crystal Specification on page 4.
Output enable pin (see OE logic state table on page 1).
Voltage Control input.
Ground.
True output LVDS (PLL502-39)
(N/C for PLL502-37)
Complementary output LVDS (PLL502-39)
(CMOS out for PLL502-37).
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
+3.3V power supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/19/06 Page 3
PLL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Crystal Pullability
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
/C
1 (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
At VCON = 1.65V
AT cut
AT cut
MIN.
12
TYP.
9.5
MAX.
25
250
30
UNITS
MHz
pF
-
Ω
Note:
Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nomi-
nal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may
reduce the pull range.
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
VCON pin input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 12 – 25MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
kΩ
kHz
500
±200
150
10
2000
25
0V
≤
VCON
≤
3.3V, -3dB
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
Output Clock
Duty Cycle
Short Circuit
Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS/CMOS
Fout<24MHz
24MHz<Fout<96MHz
96MHz<Fout<800MHz
MIN.
TYP.
MAX.
60/28/15
65/45/30
100/80/40
3.63
55
55
55
UNITS
mA
V
%
mA
2.97
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@
V
DD
– 1.3V (PECL)
45
45
45
50
50
50
±50
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/19/06 Page 4
PLL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
5. Jitter Specifications
PARAMETERS
CONDITIONS
With capacitive decoupling be-
tween VDD and GND.
Over 10,000 cycles.
FREQUENCY
19.44MHz
77.76MHz
155.52MHz
622.08MHz
19.44MHz
77.76MHz
155.52MHz
622.08MHz
155.52MHz
622.08MHz
MIN.
TYP.
2.2
4.5
4.5
5.0
17
25
27
35
2.5
2.5
MAX.
UNITS
Period jitter RMS
ps
Period jitter Peak-to-
Peak
1
With capacitive decoupling be-
tween VDD and GND.
Over 10,000 cycles.
Integrated 12 kHz to 20 MHz
ps
Integrated jitter RMS
2
4
4
ps
6. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
(typical)
FREQUENCY
19.44MHz
77.76MHz
155.52MHz
622.08MHz
@10Hz
-80
-72
-65
-55
@100Hz
-108
-103
-95
-85
@1kHz
-132
-122
-120
-109
@10kHz
-142
-130
-125
-115
@100kHz
-150
-125
-121
-110
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
7. CMOS Electrical Characteristics
PARAMETERS
Output drive current
Output Clock Rise/Fall Time
SYMBOL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
MIN.
10
10
TYP.
MAX.
UNITS
mA
mA
ns
2.4
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
When I talk to people about FPGAs , I hear a lot of people say, " I don't know how they work , " " They're too complicated , " and " I can't program them in C. " I hate to see such an amazing device g...
I've been learning about the CAN bus recently, which is based on the NXP LPC1756 chip, and the official CAN self-receiving routine. First of all, the following problem appears in the code: In the offi...
Everyone, I used the most primitive Hello world to start learning, but qmake [project] ;qmak; make; made an error, the information and code are as follows: -------------------------------------- #incl...
Does anyone know what the intelligent network system under the computer system structure is specifically about? Or what knowledge should I learn? I can't find it online, I hope an expert can answer it...
For a long time, I have always seen various discussions about single-chip microcomputers. This is not good, that is not good, that is outdated, this is advanced, and learning something is useless! Let...
Designing switching systems for testing electronic and electromechanical devices presents as many challenges as designing the products themselves. With the advent of high-speed logic in devices and co...
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
