performance and high frequency output, using a low
cost fundamental crystal of between 19-40MHz..
The frequency selector pads of PL680-3X enable
output frequencies of (2, 4, 8, or 16) * F
XIN
. The
PL680-3X is designed to address the demanding
requirements of high performance applications such
Fiber Channel, serial ATA, Ethernet, SAN, etc.
PL680-3X
2
3
4
5
GNDANA
3x3 QFN
Note1: QBAR is used for single ended CMOS output
.
Note2: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
VCO
Divider
Charge
Pump
+
Loop
Filter
Output
Divider
(1,2,4,8)
GNDBUF
LP
LM
XIN
XOUT
XTAL
OSC
Phase
Detector
VCO
(F
XiN
x16)
QBAR
Q
Performance Tuner
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 1
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
OUTPUT ENABLE LOGICAL LEVELS
Part #
PL680-38 (PECL)
PL680-37 & 39 (CMOS or LVDS)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
PIN DESCRIPTIONS
Name
VDDANA
XIN
XOUT
SEL2
OE_CTRL
DNC
GNDANA
LP
LM
GNDBUF
Q
VDDBUF
QBAR
GNDBUF
SEL1
SEL0
TSSOP
Pin number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3x3mm QFN
Pin number
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
Type
P
I
O
I
I
-
P
-
-
P
O
P
O
P
I
I
VDD for analog Circuitry.
Description
Crystal input pin. (See Crystal Specifications on page 3).
Crystal output pin. (See Crystal Specifications on page 3).
Output frequency Selector pin.
Output enable control pin. (See OE_CTRL Logic Levels on page
1).
Do Not Connect
Ground for analog circuitry.
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
GND connection for output buffer circuitry.
PECL or LVDS output.
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
Complementary PECL, LVDS output; Or single ended CMOS
output.
GND connection for output buffer circuitry.
Output frequency Selector pin.
Output frequency Selector pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 2
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
FREQUENCY SELECTION TABLE
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Selected Multiplier/Output Frequency
VCO Max*
VCO Min*
Reserved
Reserved
Fin x 2
Fin x 8
Fin x 16
Fin x 4
All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0.
* Special Test Modes to help selecting the inductor value for the target output frequency.
PERFORMANCE TUNING & INDUCTOR VALUE SELECTION
Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor
values. In addition, the chart below could be used as a reference for quick inductor value selection.
Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max”
represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output
frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are
around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency
is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock
in the middle of its tuning range with maximum margin on either side.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 3
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Crystal Shunt Capacitance
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0 (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
MIN.
19
TYP.
17.7
MAX.
40
5
30
UNITS
MHz
pF
pF
Ω
AT cut
Note:
Crystal Loading rating: 17.7pF is the loading the crystal sees from the XO chip. It is assumed that the crystal will be at nominal frequency at this
load. If the crystal requires less load to be at nominal frequency, then a capacitor can placed in series with the crystal. If the crystal requires more
load to be at nominal frequency, capacitors can be placed from XIN and XOUT to ground. This however may reduce the oscillator gain.
3. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
Output Clock
Duty Cycle
Short Circuit
Current
Note:
CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS/CMOS
PECL/LVDS
38MHz<Fout<320MHz
320MHz<Fout<640MHz
MIN.
TYP.
MAX.
65/45/30
90/70
UNITS
mA
V
%
mA
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
2.25
45
45
45
50
50
50
±50
3.63
55
55
55
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 4
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
4. Jitter Specifications
PARAMETERS
CONDITIONS
FREQUENCY
106.25MHz
156.25MHz
212.5MHz
312.5MHz
622.08MHz
106.25MHz
156.25MHz
212.5MHz
312.5MHz
622.08MHz
106.25MHz
156.25MHz
212.5MHz
312.5MHz
622.08MHz
MIN.
TYP.
0.4
0.4
0.4
0.4
0.4
3
3
3
3
6
20
20
20
20
40
MAX.
0.5
0.5
0.5
0.5
0.5
5
5
5
5
8
30
30
30
30
50
UNITS
Integrated jitter RMS
Integrated 12 kHz to 20 MHz
ps
Period jitter RMS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
ps
Period jitter Peak-to-
Peak
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
ps
5. Phase Noise Specifications
PARAMETERS
FREQ.
106.25MHz
Phase Noise
relative to carrier
(typical)
156.25MHz
212.5MHz
312.5MHz
622.08MHz
@10Hz
-66
-62
-62
-59
-49
@100Hz
-96
-92
-92
-85
-84
@1kHz
-122
-120
-118
-117
-111
@10kHz
-132
-132
-126
-128
-120
@100kHz
-126
-128
-120
-125
-118
@1M
-144
-140
-140
-139
-128
@10M
-150
-150
-150
-148
-138
dBc/Hz
UNITS
6. CMOS Electrical Characteristics
PARAMETERS
Output drive current
Output Clock Rise/Fall Time
Output Clock Rise/Fall Time
SYMBOL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
20%-80% with 50Ω Load
MIN.
30
30
TYP.
MAX.
UNITS
mA
mA
0.7
0.3
ns
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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