KMPC8245RZU400D datasheet, PDF

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KMPC8245RZU400D: DescriptionIC,MICROPROCESSOR,32-BIT,CMOS,BGA,352PIN,PLASTIC; CategoryThe embedded processor and controller Microcontrollers and processors; File Size674KB，60 Pages; ManufacturerFREESCALE (NXP)

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KMPC8245RZU400D Overview

IC,MICROPROCESSOR,32-BIT,CMOS,BGA,352PIN,PLASTIC

KMPC8245RZU400D Parametric

Parameter Name	Attribute value
Objectid	2020912471
Parts packaging code	BGA
package instruction	LBGA,
Contacts	352
Reach Compliance Code	unknown
ECCN code	3A991.A.2
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	66 MHz
External data bus width	32
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B352
length	35 mm
low power mode	YES
Number of terminals	352
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Certification status	Not Qualified
Maximum seat height	1.65 mm
speed	400 MHz
Maximum supply voltage	2.1 V
Minimum supply voltage	1.9 V
Nominal supply voltage	2 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Advance Information

MPC8245EC/D

Rev. 2, 10/2002

MPC8245

Integrated Processor

Hardware Specifications

The MPC8245 combines a MPC603e core microprocessor with a PCI bridge. The PCI support

on the MPC8245 will allow system designers to rapidly design systems using peripherals

already designed for PCI and the other standard interfaces. The MPC8245 also integrates a

high-performance memory controller which supports various types of ROM and SDRAM.

The MPC8245 is the second of a family of products that provides system-level support for

industry standard interfaces with a MPC603e processor core.

This document describes pertinent electrical and physical characteristics of the MPC8245. For

functional characteristics of the processor, refer to the

MPC8245 Integrated Processor User’s

Manual

(MPC8245UM/D).

This document contains the following topics:

Topic

Section 1.1, “Overview”

Section 1.2, “Features”

Section 1.3, “General Parameters”

Section 1.4, “Electrical and Thermal Characteristics”

Section 1.5, “Package Description”

Section 1.6, “PLL Conﬁguration”

Section 1.7, “System Design Information”

Section 1.8, “Document Revision History”

Section 1.9, “Ordering Information”

Page

To locate any published errata or updates for this document, refer to the web site at

http://www.motorola.com/semiconductors

1.1

Overview

The MPC8245 integrated processor is comprised of a peripheral logic block and a 32-bit

superscalar MPC603e core, as shown in Figure 1.

Features

The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),

memory controller, DMA controller, PIC interrupt controller, a message unit (and I

O interface), and an I

controller. The processor core is a full-featured, high-performance processor with ﬂoating-point support,

memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features.

The integration reduces the overall packaging requirements and the number of discrete devices required for

an embedded system.

The MPC8245 contains an internal peripheral logic bus that interfaces the processor core to the peripheral

logic. The core can operate at a variety of frequencies, allowing the designer to trade-off performance for

power consumption. The processor core is clocked from a separate PLL, which is referenced to the

peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different

frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus

(depending on memory data bus width) and a 32-bit address bus along with control signals that enable the

interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the

MPC8245 memory space are passed to the processor bus for snooping when snoop mode is enabled.

The processor core and peripheral logic are general-purpose in order to serve a variety of embedded

applications. The MPC8245 can be used as either a PCI host or PCI agent controller.

1.2

•

Features

Processor core

— High-performance, superscalar processor core

— Integer unit (IU), ﬂoating-point unit (FPU) (software enabled or disabled), load/store unit

(LSU), system register unit (SRU), and a branch processing unit (BPU)

— 16-Kbyte instruction cache

— 16-Kbyte data cache

— Lockable L1 caches—entire cache or on a per-way basis up to three of four ways

— Dynamic power management—supports 60x nap, doze, and sleep modes

Peripheral logic

— Peripheral logic bus

– Supports various operating frequencies and bus divider ratios

– 32-bit address bus, 64-bit data bus

– Supports full memory coherency

– Decoupled address and data buses for pipelining of peripheral logic bus accesses

– Store gathering on peripheral logic bus-to-PCI writes

— Memory interface

– Supports up to 2 Gbytes of SDRAM memory

– High-bandwidth data bus (32- or 64-bit) to SDRAM

– Programmable timing supporting SDRAM

– Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices

– Write buffering for PCI and processor accesses

– Supports normal parity, read-modify-write (RMW), or ECC

– Data-path buffering between memory interface and processor

– Low-voltage TTL logic (LVTTL) interfaces

Major features of the MPC8245 are as follows:

•

MOTOROLA

MPC8245 Integrated Processor Hardware Speciﬁcations

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