IS61NP25618-133B2I datasheet, PDF

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IS61NP25618-133B2I: DescriptionZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, PLASTIC, BGA-119; Categorystorage storage; File Size133KB，21 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/

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IS61NP25618-133B2I Overview

ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, PLASTIC, BGA-119

IS61NP25618-133B2I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	1959713729
Parts packaging code	BGA
package instruction	PLASTIC, BGA-119
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	4.2 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	4718592 bit
Memory IC Type	ZBT SRAM
memory width	18
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.41 mm
Maximum standby current	0.01 A
Minimum standby current	3.14 V
Maximum slew rate	0.305 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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IS61NP12832 IS61NP12836 IS61NP25618

IS61NLP12832 IS61NLP12836 IS61NLP25618

128K x 32, 128K x 36 and 256K x 18

PIPELINE 'NO WAIT' STATE BUS SRAM

FEATURES

•

100 percent bus utilization

No wait cycles between Read and Write

Internal self-timed write cycle

Individual Byte Write Control

Single R/W (Read/Write) control pin

Clock controlled, registered address,

data and control

Interleaved or linear burst sequence control

using MODE input

Three chip enables for simple depth expansion

and address pipelining for TQFP

Power Down mode

Common data inputs and data outputs

CKE

pin to enable clock and suspend operation

JEDEC 100-pin TQFP and 119 PBGA packages

Single +3.3V power supply (± 5%)

NP Version: 3.3V I/O Supply Voltage

NLP Version: 2.5V I/O Supply Voltage

Industrial temperature available

ISSI

NOVEMBER 2002

DESCRIPTION

The 4 Meg 'NP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 131,072 words by 32 bits, 131,072 words

by 36 bits and 262,144 words by 18 bits, fabricated with

ISSI

's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-150

3.8

6.7

150

-133

4.2

7.5

133

-100

100

Units

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. B

11/21/02

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LA4476 power amplifier circuit

Resistor-Transistor Gate Circuit

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