Freescale Semiconductor, Inc.
HC05J5AG
RE
Freescale Semiconductor, Inc...
68HC05J5A
68HRC05J5A
68HC705J5A
68HRC705J5A
SPECIFICATION
(General Release)
July 16, 1999
Semiconductor Products Sector
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
July 16, 1999
GENERAL RELEASE SPECIFIC
TABLE OF CONTENTS
Section
SECTION 1
GENERAL DESCRIPTION
1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
Freescale Semiconductor, Inc...
FEATURES ....................................................................................................
MASK OPTIONS............................................................................................
MCU STRUCTURE........................................................................................
PIN ASSIGNMENTS ......................................................................................
FUNCTIONAL PIN DESCRIPTION................................................................
V
DD
AND V
SS
............................................................................................
OSC1, OSC2/R..........................................................................................
RESET.......................................................................................................
IRQ (MASKABLE INTERRUPT REQUEST)..............................................
PA0-PA7 ....................................................................................................
PB0-PB5 ....................................................................................................
SECTION 2
MEMORY
2.1
2.2
2.3
2.4
I/O AND CONTROL REGISTERS .................................................................
RAM ...............................................................................................................
ROM...............................................................................................................
I/O REGISTERS SUMMARY .........................................................................
SECTION 3
CENTRAL PROCESSING UNIT
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
REGISTERS ..................................................................................................
ACCUMULATOR (A)......................................................................................
INDEX REGISTER (X) ...................................................................................
STACK POINTER (SP) ..................................................................................
PROGRAM COUNTER (PC) .........................................................................
CONDITION CODE REGISTER (CCR) .........................................................
Half Carry Bit (H-Bit) ..................................................................................
Interrupt Mask (I-Bit) ..................................................................................
Negative Bit (N-Bit) ....................................................................................
Zero Bit (Z-Bit) ...........................................................................................
Carry/Borrow Bit (C-Bit) .............................................................................
SECTION 4
INTERRUPTS
4.1
4.2
4.3
4.4
4.5
4.5.1
CPU INTERRUPT PROCESSING .................................................................
RESET INTERRUPT SEQUENCE ................................................................
SOFTWARE INTERRUPT (SWI) ...................................................................
HARDWARE INTERRUPTS ..........................................................................
EXTERNAL INTERRUPT (IRQ).....................................................................
IRQ CONTROL/STATUS REGISTER (ICSR) $0A....................................
REV 2.1
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Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
July 16, 1999
TABLE OF CONTENTS
Section
4.5.2
4.5.3
4.5.4
OPTIONAL EXTERNAL INTERRUPTS (PA0-PA3) ..................................
TIMER INTERRUPT (MFT) .......................................................................
TIMER1 INTERRUPT (16-BIT TIMER)......................................................
SECTION 5
RESETS
Freescale Semiconductor, Inc...
5.1
EXTERNAL RESET (RESET)........................................................................
5.2
INTERNAL RESETS ......................................................................................
5.2.1
POWER-ON RESET (POR) ......................................................................
5.2.2
COMPUTER OPERATING PROPERLY RESET (COPR).........................
5.2.3
LOW VOLTAGE RESET (LVR) .................................................................
5.2.4
ILLEGAL ADDRESS RESET (ILADR).......................................................
SECTION 6
LOW POWER MODES
6.1
6.1.1
6.1.2
6.2
6.3
6.4
STOP INSTRUCTION....................................................................................
STOP Mode ...............................................................................................
HALT Mode................................................................................................
WAIT INSTRUCTION.....................................................................................
DATA-RETENTION MODE............................................................................
COP WATCHDOG TIMER CONSIDERATIONS ...........................................
SECTION 7
INPUT/OUTPUT PORTS
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
SLOW OUTPUT FALLING-EDGE TRANSITION...........................................
PORT A..........................................................................................................
Port A Data Register..................................................................................
Port A Data Direction Register...................................................................
Port A Pulldown/up Register......................................................................
Port A Drive Capability...............................................................................
Port A I/O Pin Interrupts.............................................................................
PORT B..........................................................................................................
Port B Data Register..................................................................................
Port B Data Direction Register...................................................................
Port B Pulldown/up Register......................................................................
I/O PORT PROGRAMMING ..........................................................................
Pin Data Direction......................................................................................
Output Pin..................................................................................................
Input Pin.....................................................................................................
I/O Pin Transitions .....................................................................................
I/O Pin Truth Tables...................................................................................
ii
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MC68H
R
Freescale Semiconductor, Inc.
July 16, 1999
GENERAL RELEASE SPECIFIC
TABLE OF CONTENTS
Section
SECTION 8
MULTI-FUNCTION TIMER
8.1
8.2
8.3
8.3.1
8.3.2
8.4
8.5
Freescale Semiconductor, Inc...
OVERVIEW....................................................................................................
COMPUTER OPERATING PROPERLY (COP) WATCHDOG ......................
MFT REGISTERS ..........................................................................................
Timer Counter Register (TCR) $09............................................................
Timer Control/Status Register (TCSR) $08 ...............................................
OPERATION DURING STOP MODE ............................................................
OPERATION DURING WAIT/HALT MODE...................................................
SECTION 9
16-BIT TIMER
9.1
9.2
9.3
9.4
9.5
9.6
9.7
TIMER1 COUNTER REGISTERS (TCNTH, TCNTL) ....................................
ALTERNATE COUNTER REGISTERS (ACNTH, ACNTL)............................
INPUT CAPTURE REGISTERS ....................................................................
TIMER1 CONTROL REGISTER (T1CR) .......................................................
TIMER1 STATUS REGISTER (T1SR)...........................................................
TIMER1 OPERATION DURING WAIT MODE...............................................
TIMER1 OPERATION DURING STOP MODE ..............................................
SECTION 10
INSTRUCTION SET
10.1 ADDRESSING MODES .................................................................................
10.1.1 Inherent......................................................................................................
10.1.2 Immediate ..................................................................................................
10.1.3 Direct .........................................................................................................
10.1.4 Extended....................................................................................................
10.1.5 Indexed, No Offset.....................................................................................
10.1.6 Indexed, 8-Bit Offset ..................................................................................
10.1.7 Indexed, 16-Bit Offset ................................................................................
10.1.8 Relative......................................................................................................
10.1.9 Instruction Types .......................................................................................
10.1.10 Register/Memory Instructions ....................................................................
10.1.11 Read-Modify-Write Instructions .................................................................
10.1.12 Jump/Branch Instructions ..........................................................................
10.1.13 Bit Manipulation Instructions......................................................................
10.1.14 Control Instructions....................................................................................
10.1.15 Instruction Set Summary ...........................................................................
REV 2.1
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