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-1-
K4B4G0446B
K4B4G0846B
datasheet
History
- First SPEC release
- Corrected typo for IDD current specification "IDD4W"
- Changed timing parameters (Setup/Hold time)
- Changed Input/Output Capacitance on page 37
- Corrected Typo
Draft Date
Apr. 2011
May. 2011
Jul. 2011
Dec. 2011
Rev. 1.3
DDR3 SDRAM
Revision History
Revision No.
1.0
1.1
1.2
1.3
Remark
-
-
-
-
Editor
J.Y.Lee
J.Y.Lee
J.Y.Lee
J.Y.Lee
-2-
K4B4G0446B
K4B4G0846B
datasheet
Rev. 1.3
DDR3 SDRAM
Table Of Contents
4Gb B-die DDR3 SDRAM
1. Ordering Information ..................................................................................................................................................... 5
6. Absolute Maximum Ratings .......................................................................................................................................... 11
6.1 Absolute Maximum DC Ratings............................................................................................................................... 11
6.2 DRAM Component Operating Temperature Range ................................................................................................ 11
7. AC & DC Operating Conditions..................................................................................................................................... 11
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 11
8. AC & DC Input Measurement Levels ............................................................................................................................ 12
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12
8.3 AC & DC Logic Input Levels for Differential Signals............................................................................................... 14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 14
8.3.3. Single-ended requirements for differential signals ........................................................................................... 15
8.4 Differential Input Cross Point Voltage...................................................................................................................... 16
8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 16
8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 16
9. AC & DC Output Measurement Levels ......................................................................................................................... 17
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 17
9.2 Differential AC & DC Output Levels......................................................................................................................... 17
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 19
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 19
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 20
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 21
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 21
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 22
9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 23
9.9.1. Test Load for ODT Timings .............................................................................................................................. 24
13.1.1. Definition for tCK(avg).................................................................................................................................... 38
13.1.2. Definition for tCK(abs).................................................................................................................................... 38
13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 38
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 38
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 38
13.1.6. Definition for tERR(nper)................................................................................................................................ 38
13.2 Refresh Parameters by Device Density................................................................................................................. 39
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 39
13.3.1. Speed Bin Table Notes .................................................................................................................................. 43
-3-
K4B4G0446B
K4B4G0846B
datasheet
Rev. 1.3
DDR3 SDRAM
14. Timing Parameters by Speed Grade .......................................................................................................................... 44
14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 52
14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 59
2. Backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)
3. Backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
4. Backward compatible to DDR3-1066(7-7-7)
2. Key Features
[ Table 2 ] 4Gb DDR3 B-die Speed bins
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
DDR3-1866
13-13-13
1.07
13
13.91
13.91
34
47.91
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• V
DDQ
= 1.5V ± 0.075V
• 400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin,
667MHz f
CK
for 1333Mb/sec/pin, 800MHz f
CK
for 1600Mb/sec/pin,
900MHz f
CK
for 1866Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,12,13
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9(DDR3-1866)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
CASE
85°C, 3.9us at
85°C < T
CASE
< 95
°C
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 4Gb DDR3 SDRAM B-die is organized as a 128Mbit x 4 I/Os x 8banks
or 64Mbit x 8 I/Os x 8banks device. This synchronous device achieves high
speed double-data-rate transfer rates of up to 1866Mb/sec/pin (DDR3-
1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V
DDQ
.
The 4Gb DDR3 B-die device is available in 78ball FBGAs(x4/x8).
NOTE
: 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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