K4B4G0446B-MCH9T datasheet, PDF

Datasheet> All Categories > storage> storage> K4B4G0446B-MCH9T

K4B4G0446B-MCH9T: DescriptionDDR DRAM, 1GX4, CMOS, PBGA78,; Categorystorage storage; File Size1MB，59 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

Download Datasheet Parametric View All

K4B4G0446B-MCH9T Overview

DDR DRAM, 1GX4, CMOS, PBGA78,

K4B4G0446B-MCH9T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	1122314361
package instruction	FBGA, BGA78,9X13,32
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum clock frequency (fCLK)	667 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B78
JESD-609 code	e3
memory density	4294967296 bit
Memory IC Type	DDR3 DRAM
memory width	4
Humidity sensitivity level	1
Number of terminals	78
word count	1073741824 words
character code	1000000000
Maximum operating temperature	85 °C
Minimum operating temperature
organize	1GX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA78,9X13,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
power supply	1.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum standby current	0.024 A
Maximum slew rate	0.3 mA
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	MATTE TIN
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM

Preview

Download Datasheet

View All

K4B4G0446B

K4B4G0846B

DDP 4Gb DDR3 SDRAM

DDP 4Gb B-die DDR3 SDRAM Specification

78 FBGA with Lead-Free & Halogen-Free

(RoHS Compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Page 1 of 59

Rev. 1.0 March 2009

K4B4G0446B

K4B4G0846B

DDP 4Gb DDR3 SDRAM

Table Contents

1.0 Ordering Information ................................................................................................................... 5

2.0 Key Features ................................................................................................................................ 5

3.0 Package pinout/Mechanical Dimension & Addressing ............................................................ 6

3.1 x4 DDP Package Pinout (Top view) : 78ball FBGA Package

.............................................................. 6

3.2 x8 DDP Package Pinout (Top view) : 78ball FBGA Package

.............................................................. 7

3.3 FBGA Package Dimension (x4)

..................................................................................................... 8

3.4 FBGA Package Dimension (x8)

..................................................................................................... 9

4.0 Input/Output Functional Description ....................................................................................... 10

5.0 DDR3 SDRAM Addressing ........................................................................................................ 11

6.0 Absolute Maximum Ratings ...................................................................................................... 12

6.1 Absolute Maximum DC Ratings

................................................................................................... 12

6.2 DRAM Component Operating Temperature Range

......................................................................... 12

7.0 AC & DC Operation Conditions ................................................................................................ 12

7.1 Recommended DC operating Conditions (SSTL_1.5)

..................................................................... 12

8.0 AC & DC Input Measurement Levels ........................................................................................ 13

8.1 AC and DC Logic input levels for single-ended singnals

................................................................ 13

8.2 VREF Tolerances

....................................................................................................................... 14

8.3 AC and DC Logic Input Levels for Ditterential Signals

................................................................... 15

8.3.1 Differential signal definition

................................................................................................ 15

8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

.............................. 15

8.3.3 Single-ended requirements for differential signals

................................................................. 16

8.4 Differential Input Cross Point Voltage

.......................................................................................... 17

8.5 Slew Rate Definition for Single Ended Input Signals

...................................................................... 17

8.6 Slew rate definition for Differential Input Signals

........................................................................... 17

9.0 AC and DC Output Measurement Levels ................................................................................. 18

9.1 Single Ended AC and DC Output Levels

....................................................................................... 18

9.2 Differential AC and DC Output Levels

.......................................................................................... 18

9.3 Single Ended Output Slew Rate

................................................................................................... 18

9.4 Differential Output Slew Rate

...................................................................................................... 19

9.5 Reference Load for AC Timing and Output Slew Rate

.................................................................... 19

9.6 Overshoot/Undershoot Specification

........................................................................................... 20

9.6.1 Address and Control Overshoot and Undershoot specifications

............................................. 20

9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications

................................. 20

9.7 34 ohm Output Driver DC Electrical Characteristics

....................................................................... 21

................................................................. 22

9.8 On-Die Termination (ODT) Levels and I-V Characteristics

............................................................... 22

9.8.1 ODT DC electrical characteristics

........................................................................................ 23

9.8.2 ODT Temperature and Voltage sensitivity

............................................................................. 24

9.7.1 Output Drive Temperature and Voltage sensitivity

Page 3 of 59

Rev. 1.0 March 2009

K4B4G0446B

K4B4G0846B

9.9 ODT Timing Definitions

DDP 4Gb DDR3 SDRAM

.............................................................................................................. 25

................................................................................................. 25

9.9.2 ODT Timing Definition

........................................................................................................ 25

9.9.1 Test Load for ODT Timings

10.0 IDD Specification Parameters and Test Conditions ............................................................. 28

10.1 IDD Measurement Conditions

.................................................................................................... 28

10.2 IDD Specifications definition

..................................................................................................... 30

11.0 DDP 4Gb DDR3 SDRAM B-die IDD Spec Table ..................................................................... 37

12.0 Input/Output Capacitance ....................................................................................................... 38

13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 .............................. 39

13.1 Clock specification

............................................................................................................. 39

13.1.1 Definition for tCK (avg)

..................................................................................................... 39

13.1.2 Definition for tCK (abs)

..................................................................................................... 39

13.1.3 Definition for tCH(avg) and tCL(avg)

................................................................................... 39

13.1.4 Definition for note for tJIT(per), tJIT(per,Ick)

........................................................................ 39

...................................................................................... 39

13.1.6 Definition for tERR(nper)

................................................................................................... 39

13.2 Refresh Parameters by Device Density

....................................................................................... 40

13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

............................................. 40

13.3.1 Speed Bin Table Notes...........................................................................................................................

13.1.5 Definition for tJIT(cc), tJIT(cc,Ick)

14.0 Timing Parameters by Speed Grade ...................................................................................... 44

14.1 Jitter Notes

............................................................................................................................. 47

14.2 Timing Parameter Notes

........................................................................................................... 48

14.3 Address / Command Setup, Hold and Derating:

........................................................................... 49

14.4 Data Setup, Hold and Slew Rate Derating:

.................................................................................. 55

Page 4 of 59

Rev. 1.0 March 2009

Recommended Resources

Pure Class A Preamplifier

Music IC sound amplification circuit

Methane concentration detector circuit diagram with linearized output

IBM-PC∕XT power supply circuit diagram 03

One of the high input and high output integrated regulated power supply circuits

Adaptive pulse coding speech synthesis series

5 ways to improve temporary workers' work enthusiasm: Temporary workers are everywhere. Retail, restaurants and other industries are big employers of temporary workers, especially during the holidays. How do you motivate temporary workers? Senior experts...; ESD技术咨询 Talking about work

Can uc/os III be ported to Fpga?: uc/os iii (also known as Micriμm μC/OS-III) is a widely used embedded operating system. But even the latest Nios II Gen 2 only supports uc/os II. Does anyone know how to port the third generation to F...; dwk1234 FPGA/CPLD

Gain and Bandwidth of Voltage Feedback Operational Amplifiers: I don’t usually share anything that is not good....; gaoyang9992006 ADI Reference Circuit

Webench design prize-giving event is waiting for you to participate!: [align=left][color=#000]Just simply enter your power requirements, Duang! can complete customized power, lighting, filtering, clock and sensor designs in just a few seconds. [/color][/align][align=lef...; eric_wang TI Technology Forum

The concept of EDK (reposted): The concept of EDK (reposted) 2010-05-04 20:08　　EDK=Embedded Development Kit , embedded development kit. 　　EDK is a tool used by Xilinx to develop embedded systems. Compared with Xilinx 's ISE , the d...; wing0127 Embedded System

The BUG that has troubled me for a long time has been solved. I will share my points~ I will post this in the afternoon when I go to work: Every time I shut down my computer, WinCE would freeze. I actually solved it today. Haha, I'm so happy. I'll share the points! I'll post it at work this afternoon! :)...; hudoudou Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components