128Mb DDR SDRAM
DDR SDRAM Specification
Version 1.31
- 1 -
REV. 1.31 Nov. 3. 2001
128Mb DDR SDRAM
Revision History
Version 0 (May, 1998)
- First version for internal review
Version 0.1(June, 1998)
- Added x4 organization
Version 0.2(Sep,1998)
1. Added "Issue prcharge command for all banks of the device" as the fourth step of power-up squence.
2. In power down mode timing diagram, NOP condition is added to precharge power down exit.
Version 0.3(Dec,1998)
- Added QFC Function.
-
Added DC current value
- Reduce I/O capacitance values
Version 0.4(Feb,1999)
-Added DDR SDRAM history for reference(refer to the following page)
-Added low power version DC spec
Version 0.5(Apr,1999)
-Revised following first showing for JEDEC standard
-Added
DC target current based on new DC test condition
Version 0.6(July 1,1999)
1.Modified binning policy
From
To
-Z (133Mhz)
-Z (133Mhz/266Mbps@CL=2)
-8 (125Mhz)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz)
-0 (100Mhz/200Mbps@CL=2)
2.Modified the following AC spec values
From.
-Z
tAC
tDQSCK
tDQSQ
tDS/tDH
tCDLR
*1
tPRE
*1
tRPST
*1
tHZQ
*1
*1
To.
-0
+/- 1ns
+/- 1ns
+/- 0.75ns
0.75 ns
2.5tCK-tDQSS
1tCK +/- 1ns
tCK/2 +/- 1ns
tCK/2 +/- 1ns
-Z
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-Y
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-0
+/- 0.8ns
+/- 0.8ns
+/- 0.6ns
0.6 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/-0.8ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
2.5tCK-tDQSS
1tCK +/- 0.75ns
tCK/2 +/- 0.75ns
tCK/2 +/- 0.75ns
: Changed description method for the same functionality. This means no difference from the previous version.
3.Changed the following AC parameter symbol
Output data access time from CK/CK
tAC
Version 0.61(August 9,1999)
- Changed the some values of "write with auto precharge" table for different bank in page 31.
From.
tDQCK
To.
Asserted
command
Old
Read
Read + AP
*1
Legal
Legal
For Different Bank
3
New
Illegal
Illegal
Old
Legal
Legal
4
New
Illegal
Illegal
- 2 -
REV. 1.31 Nov. 3. 2001
128Mb DDR SDRAM
Revision History(continued)
Version 0.7 (March, 2000)
- Changed 128Mb spec from target to Preliminary version.
- Changed partnames as follows.
from
KM44L32031BT-G(L)Z/Y/0
KM48L16031BT-G(L)Z/Y/0
KM416L8031BT-G(L)Z/Y/0
- Changed input cap. spec.
from
CK/CK
DQ/DQS/DM
CMD/Addr
2.5pF ~ 3.5pF
4.0pF ~ 5.5pF
2.5pF ~ 3.5pF
to
2.0pF ~ 3.0pF w/ Delta Cin = 0.25pF
4.0pF ~ 5.0pF w/ Delta Cin = 0.5pF
2.0pF ~ 3.0pF with Delta Cin = 0.5pF
to
K4H280438B-TC(L)A2/B0/A0
K4H280838B-TC(L)A2/B0/A0
K4H281638B-TC(L)A2/B0/A0
- Changed operating condition.
from
Vil/Vih(ac)
V
IL
/V
IH
(dc)
Vref +/- 0.35V
Vref +/- 0.18V
to
Vref +/- 0.31V
Vref +/- 0.15V
- Added Overshoot/Undershoot spec
. Vih(max) = 4.2V, the overshoot voltage duration is
≤
3ns at VDD.
. Vil(min) =- 1.5V, the overshoot voltage duration is
≤
3ns at VSS.
- Changed AC parameters as follows.
from
tDQSQ
tDV
tQH
tHP
- Added DC spec values.
Version 0.71 (April, 2000)
- Corrected a typo for tRAS at 133Mhz/CL2.5 from 48ns t0 45ns.
- Corrected a typo in "General Information" table from 64Mx4 to 8Mx16.
Version 0.72(May,2000)
-
Changed DC spec item & test condition
Version 0.73(June,2000)
-
Added updated DC spec values
-
Deleted tDAL in AC parameter
Version 1.0(July,2000)
-
Eliminate "preliminary"
+/- 0.5(PC266), +/- 0.6(PC200)
+/- 0.35tCK
-
-
to
+0.5(PC266), +0.6(PC200)
-
tHPmin - 0.75ns(PC266)
tHPmin - 1.0ns(PC200)
tCLmin or tCHmin
New Definition
Removed
New Definition
Comments
- 3 -
REV. 1.31 Nov. 3. 2001
128Mb DDR SDRAM
Version 1.1(February,2001)
-
Updated DC current value.
- Changed V
I D
(DC), Input differential voltage, CK and CK inputs min. from 0.3V to 0.36V.
- Added V
IX
(DC), Input crossing point voltage, CK and CK inputs to 1.15V ~1.35V.
- Added Output high/low current(I
O H
,I
OL
) for half strength driver.
- Added Pullup current to pulldown current ratio to 0.71 ~ 1.4.
- Changed V
I D
(AC), Input differential voltage, CK and CK inputs min. from 0.62V to 0.7V.
- Changed tCK max from 15ns to 12ns for all speed binning.
- Changed tDQSH/tDQSL min. from 0.4tCK to 0.35tCK.
- Added tHZ/tLZ(Data-out high/Low impedence time from CK/CK)
- Added tQHS(Data hold skew factor)
Version 1.2(February,2001)
- Added tDSS/tDSH(DQS falling edge to/from CK rising - setup/hold time)
- Added overshoot/undershoot spec
Version 1.21(March,2001)
- Added tSL(I), tSL(IO), tSL(O)
Parameter
tSL(I)
tSL(IO)
tSL(O)
tSL(O)
Definition
Min.
Input Slew Rate(for input only)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
Output Slew Rate(x16)
0.5
0.5
1.0
0.7
Value
Max.
Unit
V/ns
V/ns
4.5
5
V/ns
V/ns
Version 1.22(March,2001)
- Changed from supporting QFC function to not supporting QFC function(Deleted all QFC function supported)
- Changed name and specification from IDD7 to IDD7A
Description
Orerating current - Four bank operation
from
IDD7(50% of data changing at every burst)
to
IDD7(100% of data changing at every burst)
Version 1.23(July,2001)
- Add derating values for the specifications if the single-ended clock skew rate is less than 1.0V/ns in page 49.
Version 1.24(August,2001)
-Fixed incorrect value of table in page 31, ’write with auto precharge’.
- 4 -
REV. 1.31 Nov. 3. 2001
128Mb DDR SDRAM
Version 1.3(October,2001)
- Modificated typo.
- Changed pin # 17 from NC to A13 in Package pinout.
- Revised "Write with autoprecharge" table in page 29.
- Added tIS and tPDEX parameters in "power down" timing of page 31.
- Revised "Absolute maximum rating" table in page 38.
. Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V
. Changed "power dissipation" value from 1.0W to 1.5W.
- Revised AC parameter table
From
DDR266A
Min.
tHZ(DQ)
tACmin
-400ps
tACmin
-400ps
Max.
tACmax
-400ps
tACmax
-400ps
DDR266B
Min.
tACmin
-400ps
tACmin
-400ps
Max.
tACmax
-400ps
tACmax
-400ps
DDR200
Min.
tACmin
-400ps
tACmin
-400ps
Max.
tACmax
-400ps
tACmax
-400ps
DDR266A
Min.
-0.75
Max.
+0.75
To
DDR266B
Min.
-0.75
Max.
+0.75
DDR200
Min.
-0.8
Max.
+0.8
tLZ(DQ)
tHZ(DQS)
tLZ(DQS)
tWPST
(tCK)
tPDEX
-0.75
-0.75
-0.75
+0.75
+0.75
+0.75
0.6
-0.75
-0.75
-0.75
0.4
7.5ns
+0.75
+0.75
+0.75
0.6
-0.8
-0.8
-1.1
0.4
10ns
+0.8
+0.8
-0.8
0.6
0.25
10ns
0.25
10ns
0.25
10ns
0.4
7.5ns
Version 1.31(November,2001)
- Deleted tHZ/tLZ of DQS
- 5 -
REV. 1.31 Nov. 3. 2001
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