K4S28323LE-DC1H datasheet, PDF

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K4S28323LE-DC1H: DescriptionSynchronous DRAM, 4MX32, 7ns, CMOS, PBGA90; Categorystorage storage; File Size81KB，10 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K4S28323LE-DC1H Overview

Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90

K4S28323LE-DC1H Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	104351848
Reach Compliance Code	compliant
ECCN code	EAR99
YTEOL	2
Maximum access time	7 ns
Maximum clock frequency (fCLK)	105 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PBGA-B90
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	32
Number of terminals	90
word count	4194304 words
character code	4000000
Maximum operating temperature	70 °C
Minimum operating temperature	-25 °C
organize	4MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA90,9X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	4096
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.0005 A
Maximum slew rate	0.14 mA
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM

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K4S28323LE-S(D)E/N/S/C/L/R

1M x 32Bit x 4 Banks SDRAM in 90FBGA

FEATURES

•

2.5V power supply

LVCMOS compatible with multiplexed address

Four banks operation

MRS cycle with address key programs

- CAS latency (1, 2 & 3)

- Burst length (1, 2, 4, 8 & Full page)

- Burst type (Sequential & Interleave)

Special Function Support

- Internal TCSR(Temperature Compensated Self Refresh)

- PASR(Partial Array Self Refresh)

All inputs are sampled at the positive going edge of the system

clock

Burst read single-bit write operation

DQM for masking.

Auto & self refresh

64ms refresh period (4K cycle).

Extended Temperature Operation (-25

°C

~ 85°C).

Commercial Temperature Operation (-25

°C

~ 70

°C).

90Balls Monolithic FBGA(11mm x 13mm)

Pb for -SXXX, Pb Free for -DXXX.

Mobile-SDRAM

GENERAL DESCRIPTION

The K4S28323LE is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 1,048,576 words by 32

bits, fabricated with SAMSUNG′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock and I/O transactions are possible

on every clock cycle. Range of operating frequencies, program-

mable burst lengths and programmable latencies allow the

same device to be useful for a variety of high bandwidth and

high performance memory system applications.

•

ORDERING INFORMATION

Part No.

Max Freq.

Interface Package

K4S28323LE-S(D)E/N/S/C/L/R60 166MHz(CL=3)

133MHz(CL=3)

90FBGA

105MHz(CL=2) LVCMOS

K4S28323LE-S(D)E/N/S/C/L/R1H 105MHz(CL=2)

(Pb Free)

K4S28323LE-S(D)E/N/S/C/L/R75

K4S28323LE-S(D)E/N/S/C/L/R1L 105MHz(CL=3)

- S(D)E/N/S : Normal/Low/Super Low Power, Extended Temp.

- S(D)C/L/R : Normal/Low/Super Low Power, Commercial Temp.

Note :

1. In case of 40MHz Frequency, CL1 can be supported.

FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE

Data Input Register

LDQM

Bank Select

1M x 32

Refresh Counter

Output Buffer

Row Decoder

Sense AMP

Row Buffer

DQi

Address Register

CLK

ADD

Column Decoder

Col. Buffer

LRAS

LCBR

Latency & Burst Length

LCKE

LRAS

LCBR

LWE

LCAS

Programming Register

LWCBR

LDQM

Timing Register

CLK

CKE

RAS

CAS

DQM

* Samsung Electronics reserves the right to change products or specification without notice.

May. 2003

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