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K4S28323LE-SL1L

Description
Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90
Categorystorage    storage   
File Size81KB,10 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

K4S28323LE-SL1L Overview

Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90

K4S28323LE-SL1L Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid104351829
Reach Compliance Codecompliant
ECCN codeEAR99
YTEOL2
Maximum access time7 ns
Maximum clock frequency (fCLK)105 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PBGA-B90
JESD-609 codee0
memory density134217728 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width32
Number of terminals90
word count4194304 words
character code4000000
Maximum operating temperature70 °C
Minimum operating temperature-25 °C
organize4MX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA90,9X15,32
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
power supply2.5 V
Certification statusNot Qualified
refresh cycle4096
Continuous burst length1,2,4,8,FP
Maximum standby current0.0005 A
Maximum slew rate0.12 mA
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
K4S28323LE-S(D)E/N/S/C/L/R
1M x 32Bit x 4 Banks SDRAM in 90FBGA
FEATURES
2.5V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS latency (1, 2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
Special Function Support
- Internal TCSR(Temperature Compensated Self Refresh)
- PASR(Partial Array Self Refresh)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking.
Auto & self refresh
64ms refresh period (4K cycle).
Extended Temperature Operation (-25
°C
~ 85°C).
Commercial Temperature Operation (-25
°C
~ 70
°C).
90Balls Monolithic FBGA(11mm x 13mm)
Pb for -SXXX, Pb Free for -DXXX.
Mobile-SDRAM
GENERAL DESCRIPTION
The K4S28323LE is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth and
high performance memory system applications.
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
K4S28323LE-S(D)E/N/S/C/L/R60 166MHz(CL=3)
133MHz(CL=3)
90FBGA
105MHz(CL=2) LVCMOS
Pb
K4S28323LE-S(D)E/N/S/C/L/R1H 105MHz(CL=2)
(Pb Free)
K4S28323LE-S(D)E/N/S/C/L/R75
K4S28323LE-S(D)E/N/S/C/L/R1L 105MHz(CL=3)
*1
- S(D)E/N/S : Normal/Low/Super Low Power, Extended Temp.
- S(D)C/L/R : Normal/Low/Super Low Power, Commercial Temp.
Note :
1. In case of 40MHz Frequency, CL1 can be supported.
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
1M x 32
1M x 32
1M x 32
1M x 32
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
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