5962R9582401VQC datasheet, PDF

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5962R9582401VQC: Description8-BIT, 2MHz, MICROPROCESSOR, CDIP40, SIDE BRAZED, METAL SEALED, CERAMIC, DIP-40; CategoryThe embedded processor and controller Microcontrollers and processors; File Size743KB，16 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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5962R9582401VQC Overview

8-BIT, 2MHz, MICROPROCESSOR, CDIP40, SIDE BRAZED, METAL SEALED, CERAMIC, DIP-40

5962R9582401VQC Parametric

Parameter Name	Attribute value
Parts packaging code	DIP
package instruction	DIP,
Contacts	40
Reach Compliance Code	unknow
ECCN code	3A001.A.2.C
Address bus width	16
bit size	8
boundary scan	NO
maximum clock frequency	4 MHz
External data bus width	8
Format	FIXED POINT
Integrated cache	NO
JESD-30 code	R-CDIP-T40
JESD-609 code	e4
low power mode	YES
Number of terminals	40
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	5.72 mm
speed	2 MHz
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
total dose	100k Rad(Si) V
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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DUC

PRO PRODU

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UTE

r at

OBS UBSTIT H or

e n te c

Data

S-80C86 Support C com/ts

IBLE

Sheet

O SS

ic a

e r s il

e c h n w w w .in t

our T

t a c t E R S IL o

8 - IN T

1- 88

HS-80C85RH

August 2000

File Number

3036.3

Radiation Hardened 8-Bit CMOS

Microprocessor

The HS-80C85RH is an 8-bit CMOS microprocessor

fabricated using the Intersil radiation hardened self-aligned

junction isolated (SAJI) silicon gate technology. Latch-up

free operation is achieved by the use of epitaxial starting

material to eliminate the parasitic SCR effect seen in

conventional bulk CMOS devices.

The HS-80C85RH is a functional logic emulation of the

HMOS 8085 and its instruction set is 100% software

compatible with the HMOS device. The HS80C85RH is

designed for operation with a single 5 volt power supply. Its

high level of integration allows the construction of a radiation

hardened microcomputer system with as few as three ICs

(HS-80C85RH CPU, HS83C55RH ROM I/O, and the

HS-81C55/56RH RAM I/O.

Specifications for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed here must be used when ordering.

Detailed Electrical Specifications for these devices are

contained in SMD 5962-95824. A “hot-link” is provided

on our homepage for downloading.

www.intersil.com/spacedefense/space.asp

Features

• Electrically Screened to SMD # 5962-95824

• QML Qualified per MIL-PRF-38535 Requirements

• Radiation Hardened EPI-CMOS

- Parametrics Guaranteed . . . . . . . . . . . 1 x 10

RAD(Si)

- Transient Upset . . . . . . . . . . . . . . . . >1 x 10

RAD(Si)/s

- Latch-up Free . . . . . . . . . . . . . . . . . >1 x 10

RAD(Si)/s

• Low Standby Current . . . . . . . . . . . . . . . . . . . . 500µA Max

• Low Operating Current. . . . . . . . . . 5.0mA/MHz (X

Input)

• Electrically Equivalent to Sandia SA 3000

• 100% Software Compatible with INTEL 8085

• Operation from DC to 2MHz, Post Radiation

• Single 5V Power Supply

• On-Chip Clock Generator and System Controller

• Four Vectored Interrupt Inputs

• Completely Static Design

• Self Aligned Junction Isolated (SAJI) Process

• Military Temperature Range. . . . . . . . . . . -55

C to 125

Ordering Information

ORDERING NUMBER

5962R9582401QQC

5962R9582401QXC

5962R9582401VQC

5962R9582401VXC

HS9-80C85RH/Proto

INTERNAL

MKT. NUMBER

HS1-80C85RH-8

HS9-80C85RH-8

HS1-80C85RH-Q

HS9-80C85RH-Q

HS9-80C85RH/Proto

TEMP. RANGE

(

-55 to 125

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a registered trademark of Intersil Americas Inc.

HS-80C85RH

Pin Description

SYMBOL

A8 - A15

AD0-7

NUMBER

21-28

12-19

TYPE

I/O

DESCRIPTION

Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,

three-stated during Hold and Halt modes and during RESET.

Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the bus

during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second

and third clock cycles.

Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the address

to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guarantee setup and

hold times for the address information. The falling edge of ALE can also be used to strobe the status

information. ALE is never three-stated.

Machine Cycle Status:

IO/M

STATUS

Memory write

I/O write

I/O read

Opcode fetch

Interrupt acknowledge

Halt

Hold

Reset

ALE

S0, S1, and

IO/M

31, 35,

and 36

T = three-State (high impedance)

X = Unspecified

S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of a machine

cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of

these lines.

Read Control: A low level on RD indicates the selected memory or I/O device is to be read and that the

Data Bus is available for the data transfer, three-stated during Hold and Halt modes and during RESET.

Write Control: A low level on WR indicates the data on the Data Bus is to be written into the selected

memory or I/O location. Data is set up at the trailing edge of WR, three-stated during Hold and Halt modes

and during RESET.

Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready

to send or receive data. If READY is low, the CPU will wait an integral number of clock cycles for READY

to go high before completing the read or write cycle. READY must conform to specified setup and hold

times.

Hold: Indicates that another master is requesting the use of the address and data buses. The CPU, upon

receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus

transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is

removed. When the HOLD is acknowledged, the Address, Data Bus, RD, WR, and IO/M lines are

3-stated.

Hold Acknowledge: Indicates that the CPU has received the HOLD request and that it will relinquish the

bus in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the bus

one half clock cycle after HLDA goes low.

Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to the last

clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will

be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL

instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by

software. It is disabled by Reset and immediately after an interrupt is accepted.

READY

HOLD

HLDA

INTR

HS-80C85RH

Pin Description

SYMBOL

INTA

RST 5.5

RST 6.5

RST 7.5

TRAP

(Continued)

TYPE

DESCRIPTION

Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruction cycle

after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some other interrupt port.

Restart Interrupts: These three inputs have the same timing as INTR except they cause an internal

RESTART to be automatically inserted.

The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher priority than

INTR. In addition, they may be individually masked out using the SIM instruction.

Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as INTR or

RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.

(See Table 6.)

Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops. The data

and address buses and the control lines are three-stated during RESET and because of the

asynchronous nature of RESET the processor’s internal registers and flags may be altered by RESET

with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C network

for power-on RESET delay (see Figure 1). Upon power-up, RESET IN must remain low for at least 10

“clock cycle” after minimum VDD has been reached. For proper reset operation after the power-up

duration, RESET IN should be kept low a minimum of three clock periods. The CPU is held in the reset

condition as long as RESET IN is applied.

Reset Out: Reset Out indicates CPU is being reset. Can be used as a system reset. The signal is

synchronized to the processor clock and lasts an integral number of clock periods.

X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator. X, can

also be an external clock Input from a logic gate. The input frequency is divided by 2 to give the

processor’s internal operating frequency.

Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.

Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM instruction

is executed.

Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.

Power: +5V supply.

Ground: Reference.

NUMBER

RESET IN

RESET OUT

CLK

SID

SOD

VCC

GND

RESET IN

VDD

TYPICAL POWER-ON RESET RC VALUES (NOTE)

R1 = 75kΩ

C1 = 1µF

NOTE: Values may have to vary due to applied power supply ramp up time.

FIGURE 1. POWER-ON RESET CIRCUIT

5962R9582401VQC Related Products

	5962R9582401VQC	5962R9582401VXC
Description	8-BIT, 2MHz, MICROPROCESSOR, CDIP40, SIDE BRAZED, METAL SEALED, CERAMIC, DIP-40	8-BIT, 2MHz, MICROPROCESSOR, CDFP42, METAL SEALED, CERAMIC, DFP-42
Parts packaging code	DIP	DFP
package instruction	DIP,	DFP,
Contacts	40	42
Reach Compliance Code	unknow	unknown
ECCN code	3A001.A.2.C	3A001.A.2.C
Address bus width	16	16
bit size	8	8
boundary scan	NO	NO
maximum clock frequency	4 MHz	4 MHz
External data bus width	8	8
Format	FIXED POINT	FIXED POINT
Integrated cache	NO	NO
JESD-30 code	R-CDIP-T40	R-CDFP-F42
JESD-609 code	e4	e4
low power mode	YES	YES
Number of terminals	40	42
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DFP
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	FLATPACK
Certification status	Not Qualified	Not Qualified
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
Maximum seat height	5.72 mm	2.54 mm
speed	2 MHz	2 MHz
Nominal supply voltage	5 V	5 V
surface mount	NO	YES
technology	CMOS	CMOS
Temperature level	MILITARY	MILITARY
Terminal surface	GOLD	GOLD
Terminal form	THROUGH-HOLE	FLAT
Terminal pitch	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL
total dose	100k Rad(Si) V	100k Rad(Si) V
width	15.24 mm	16.255 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR
Base Number Matches	1	1

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