I/O Circuit Type ....................................................................................................................................... 35
12. Example Characteristics ....................................................................................................................... 193
19. Major Changes ...................................................................................................................................... 228
Document Number: 002-04662 Rev. *H
Page 4 of 281
CY91520 Series
1.
Product Lineup
CY91F523B
CY91F524B
CY91F525B
On chip PLL Clock multiple method
12.5 ns (80 MHz)
(256+64) KB
(384+64) KB
(512+64) KB
(768+64) KB
64 KB
(48+8) KB
(64+8) KB
(96+8) KB
CY91F522B
CY91F526B
Product Lineup Comparison 64 Pins
System Clock
Minimum instruction execution time
Flash Capacity (Program)
(1024+64) KB
Flash Capacity (Data)
RAM Capacity
(128+8) KB
External BUS I/F
None
(22 address/16 data/4 cs)
DMA Transfer
16 ch
16-bit Base Timer
None
Free-run Timer
16 bit × 3 ch, 32 bit × 1 ch
Input capture
16 bit × 4 ch, 32 bit × 5 ch
Output Compare
16 bit × 6 ch, 32 bit × 4 ch
16-bit Reload Timer
7 ch
PPG
16 bit × 21 ch
Up/down Counter
2 ch
Clock Supervisor
Yes
External Interrupt
8 ch × 2 units
A/D converter
12 bit × 13 ch (1 unit), 12 bit × 13 ch (1 unit)
D/A converter (8 bit)
1 ch
Multi-Function Serial Interface
8 ch
*1
CAN
64 msg × 2 ch/128 msg × 1 ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
44 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6 ch
NMI request function
Yes
Operation guaranteed temperature (T
A
)
-40 °C to +125 °C
Power supply
2.7 V to 5.5 V
*2
Package
LQD064
2
C (standard mode).
*1: Only channel 5, channel 6 and channel 11 support the I
*2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
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