Freescale Semiconductor
Advance Information
Document Number: MC33897
Rev. 15.0, 10/2006
Single Wire CAN Transceiver
The 33897 Series provides a physical layer for digital
communications purposes using a Carrier Sense Multiple Access/
Collision Resolution (CSMA/CR) data link operating over a single
wire medium. This is more commonly referred to as Single Wire
Controller Area Network (CAN).
The 33897 Series operates directly from a vehicle's 12 V battery
system or a broad range of DC-power sources. It can operate at
either low or high (33.33 kbps or 83.33 kbps) data rates. A high-
voltage wake-up feature allows the device to control the regulator
used in support of the MCU and other logic. The device includes a
control terminal that can be used to put the module regulator into
Sleep mode. The presence of a defined wake-up voltage level on the
bus will reactivate the control line to turn the regulator and the system
back on.
The device complies with the GMW3089v2.4 General Motors
Corporation specification.
Features
•
•
•
•
•
•
•
•
Waveshaping for Low Electromagnetic Interference (EMI)
Detects and Automatically Handles Loss of Ground
Worst-Case Sleep Mode Current of Only 60
µA
(75
µA
on the 33897T)
Current Limit Prevents Damage Due to Bus Shorts
Built-In Thermal Shutdown on Bus Output
Protected Against Vehicular Electrical Transients
Undervoltage Lockout Prevents False Data with Low Battery
Pb-Free Packaging Designated by Suffix Code EF
33897/A/B/C/D/T
SINGLE WIRE CAN
TRANSCEIVER
D SUFFIX
EF (PB-FREE) SUFFIX
98ASB42565B
14-TERMINAL SOICN
EF (PB-FREE) SUFFIX
98ASB42564B
8-TERMINAL SOICN
ORDERING INFORMATION
Contains Lead
MC33897D/R2
MC33897AD/R2
Pb-Free
MC33897EF/R2
MC33897AEF/R2
RoHS
MCZ33897EF/R2
MCZ33897TEF/R2
MCZ33897AEF/R2
*MCZ33897CEF/R2
MC33897BEF/R2
MCZ33897BEF/R2
*MCZ33897DEF/R2
*Recommended device for all new designs
8 SOICN
- 40°C to 125°C
14 SOICN
Temperature
Range (T
A
)
Package
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Power
Source
VCC
Voltage
Regulator
EN
Battery
VBATT
VCC
CNTL
TXD
RXD
MCU
MODE0
MODE1
GND
4
BUS
LOAD
SWC BUS
33897/A/C/T
Figure 1. 33897/A/C Simplified Application Diagram
VCC
Battery
VCC
TXD
RXD
MCU
VBATT
BUS
LOAD
SWC BUS
MODE0
MODE1
GND
33897B/D
Figure 2. 33897B/D Simplified Application Diagram
33897/A/B/C/D/T
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Part No.
33897
1.0 V Max
33897T
Load Voltage Sleep
Mode
•
•
•
•
•
33897A
•
•
•
33897B
•
•
•
0.1 V Max
*33897C
•
•
•
•
•
•
*33897D
•
•
•
14-Pin Package
14-Pin Package
Quiescent Current in Sleep Mode, 5.0V
∠
V
ΒΑΤΤ
∠
13V, Typical - 55
µA,
Max - 75µA
ESD Voltage: Machine Model
±100V
14-Pin Package
Removes diode drop during Sleep Mode
May not detect Loss of Ground under certain module characteristics.
8-Pin Package
Removes diode drop during Sleep Mode
Does not include the CNTL terminal
May not detect Loss of Ground under certain module characteristics.
14-Pin Package
Removes diode drop during Sleep Mode
Effectively detects Loss of Ground
ESD Voltage: Human Body Model
±1500V,
Machine Model
±100V
8-Pin Package
Removes diode drop during Sleep Mode
Effectively detects Loss of Ground
Does not include the CNTL terminal
ESD Voltage: Human Body Model
±1500V,
Machine Model
±100V
2, 4, 6, 7, 8 ,13, 16
8
2, 4, 6, 7, 8 ,13, 16
8
Other Significant Differences
See Page
8
6, 7, 8
*Recommended device for all new designs
33897/A/B/C/D/T
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
TXD
Bus DRVR
TX
BUS DRVR
MODE0
MODE1
HV WU E n
HVWU Enable
Mode
Mode
Co ntrol
Control
Wa ve Sha ping E n
Waveshaping Enable
TX Dat
Data
TXD
a
BUS
Disab le
Disable
Bus RCVR
BUS RCVR
HVWU
De t
HV WU
Detect
RX Dat a
RXD Data
Disab le
Disable
TXD
RXD
Undervoltage
Detect
Timer
OSC
Load Switch
VBATT
BAT
Timers
LOAD
GND
CNTL
CNTL*
*CNTL terminal is present on 33897/A/C/T only.
Figure 3. 33897/A/B/C/D/T Simplified Internal Block Diagram
33897/A/B/C/D/T
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
33897/A/C/T
GND
TXD
MODE0
MODE1
RXD
NC
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
GND
NC
BUS
LOAD
VBATT
CNTL
GND
TXD
MODE0
MODE1
RXD
1
1
2
2
3
3
4
4
33897B/D
8
8
7
7
6
6
5
5
GND
BUS
LOAD
VBATT
Figure 4. 33897/A/B/C/D/T Pin Connections
Table 2. Pin Definitions
A functional description of each terminal can be found in the Functional Pin Description section, beginning on page
13.
33897/A/C/T
Terminal
1, 7, 8, 14
33897B/D
Terminal
8
Pin Name
GND
Formal Name
Ground
Definition
Electrical Common Ground and Heat removal. A good thermal path
will also reduce the die temperature.
Data input here will appear on the BUS terminal. A logic [0] will assert
the bus, a logic [1] will make the bus go to the recessive state.
These Pins control Sleep Mode, Transmit Level, and Speed. They
have weak pulldowns.
Open drain output of the data on BUS. A recessive bus = a logic [1], a
dominant bus = logic [0]. An external pullup is required.
No internal connection to these Pins. Pin 13 can be connected to GND
to allow the use of the 14-terminal or 8-terminal device.
(1)
Provides a battery-level logic signal.
Power input. An external diode is needed for reverse battery
protection.
The external bus load resistor connects here to prevent bus pullup in
the event of loss of module ground.
This terminal connects to the bus through external components.
2
1
TXD
Transmit Data
3, 4
2, 3
MODE0,
MODE1
RXD
Mode Control
5
4
Receive Data
6, 13
–
NC
No Connect
9
10
–
5
CNTL
VBATT
Control
Battery
11
6
LOAD
Load
12
7
BUS
Bus
Notes
1. Module boards can be planned for the 14-terminal package and still use the 8-terminal package.
33897/A/B/C/D/T
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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