ADD8754 datasheet, PDF - EEWORLD Datasheet

LCD Panel Power, V

COM

,

and

G

ate Modulation

ADD8754

FEATURES

Step-up switching regulator with 2 A power switch

650 kHz or 1.2 MHz switching frequency

Output adjustable to 20 V

350 mA logic voltage regulator

Selectable output voltages: 2.5 V, 2.85 V, 3.3 V

V

COM

amplifier with 300 mA drive

Gate pulse modulation circuitry

Independently adjustable delay and falling slope

General

3 V to 5.5 V input

Undervoltage lockout

Thermal shutdown

24-lead, Pb-free LFCSP package

FUNCTIONAL BLOCK DIAGRAM

COMP

SS

VIN_1 VIN_2

ADD8754

FB

FREQ

SHDN

STEP-UP SWITCHING

REGULATOR

LX

UNDER VOLTAGE LOCKOUT

AND THERMAL PROTECTION

LOGIC VOLTAGE

REGULATOR

LDO_OUT

ADJ

VDD_2

OUT

VCOM AMPLIFIER

POS

NEG

APPLICATIONS

TFT LCD panels for monitors, TVs, and notebooks

VGH

GATE PULSE

MODULATION

05110-001

VGH_M VDD_1 CE RE VFLK

VDPM

Figure 1.

GENERAL DESCRIPTION

The ADD8754 is optimized for use in TFT LCD applications,

requiring only external charge pump components to provide all

the requirements for panel power, V

COM

, and gate modulation.

Included in a single chip are a high frequency step-up dc-to-dc

switching regulator, logic voltage regulator, V

COM

amplifier, and

gate pulse modulation circuitry.

The step-up dc-to-dc converter provides up to 20 V output and

includes a 2 A internal switch. Either a 650 kHz or 1.2 MHz step-

up switching regulator frequency can be chosen, allowing easy

filtering and low noise operation. It achieves 93% efficiency and

features soft start to limit the inrush current at startup.

The internal voltage regulator operates with an input voltage

range of 3 V to 5.5 V and delivers a load current of up to

350 mA. Three selectable output voltages are available: 2.5 V,

2.85 V, and 3.3 V.

The proprietary V

COM

amplifier can deliver a peak output

current of 300 mA and is specifically designed to drive TFT

panel loads.

The gate pulse modulator allows shaping of the TFT gate high

voltage to improve image quality. The integrated switches

provide the ability to independently control the delay and slope

for the gate drive voltage.

The ADD8754 is offered in a 24-lead, Pb-free LFCSP package and

is specified over the industrial temperature range of −40 to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

ADD8754

TABLE OF CONTENTS

Specifications..................................................................................... 3

Step-Up Switching Regulator Specifications............................. 3

LDO Regulator Specifications .................................................... 4

V

COM

Amplifier Specifications .................................................... 5

Gate Pulse Modulator Specifications ......................................... 6

General Specifications ................................................................. 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

Current-Mode, Step-Up Switching Regulator Operation..... 12

V

COM

Amplifier ........................................................................... 16

Gate Pulse Modulator Circuit................................................... 16

Power-Up Sequence ................................................................... 17

Shutdown..................................................................................... 17

UVLO........................................................................................... 17

Power Dissipation....................................................................... 18

Layout Guidelines....................................................................... 19

Typical Application Circuits ......................................................... 20

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

4/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

ADD8754

SPECIFICATIONS

STEP-UP SWITCHING REGULATOR SPECIFICATIONS

VIN_1 = VIN_2 = SHDN = 5 V, V

OUT1

= VDD_1 = VDD_2 = 14 V, T

A

= 25°C, FREQ = GND, unless otherwise noted.

Table 1.

Parameter

SUPPLY

Input Voltage Range

OUTPUT

1

Output Voltage Range

Load Regulation

Line Regulation

Load Regulation

Line Regulation

Overall Regulation

REFERENCE

Feedback Voltage

ERROR AMPLIFIER

Transconductance

Gain

Input Bias Current

SWITCH

On Resistance

Leakage Current

Peak Current Limit

OSCILLATOR

Oscillator Frequency

Maximum Duty Cycle

SOFT START

Peak Current

1

Symbol

VIN

V

OUT1

Conditions

Min

3.0

Typ

Max

5.5

20

Unit

V

μV/mA

mV

μV/mA

mV

%

V

μA/V

V/V

nA

mΩ

μA

A

kHz

MHz

%

μA

10 mA ≤ I

LOAD

≤ 150 mA, V

OUT1

= 10 V

I

LOAD

= 350 mA, 4.5 V ≤ VIN_1 ≤ 5.5 V

10 mA ≤ I

LOAD

≤ 150 mA, V

OUT1

= 10 V

I

LOAD

= 150 mA, 3.0 V ≤ VIN_1 ≤ 5.5 V

Line, load, temperature (−40°C ≤ T

A

≤ +85°C)

VFB

G

MEA

A

V

I

B

R

DS (ON)

I

LKG

I

CL

F

OSC

D

MAX

200

−3

1.200

1.211

100

1000

225

170

0.5

2.6

650

1.2

90

2.5

+3

1.220

V

LX

= 14 V, SHDN = GND

FREQ = GND

FREQ = VIN_1

VFB = 1 V

SS = GND

95

Refer to the Figure 23.

Rev. 0 | Page 3 of 28

ADD8754

LDO REGULATOR SPECIFICATIONS

VIN_1 = VIN_2 = SHDN = 5 V, ADJ = LDO_OUT,

1

CLDO = 2.2 μF, T

A

= 25°C, unless otherwise noted.

Table 2.

Parameter

INPUT

Input Voltage Range

Symbol

VIN

2

Conditions

ADJ = LDO_OUT

1

ADJ = OPEN

3

ADJ = GND

4

OUTPUT

Output Voltage

LDO_OUT

I

LDO

= 1 mA, ADJ = GND

I

LDO

= 350 mA, ADJ = GND

I

LDO

= 1 mA, ADJ = OPEN

I

LDO

= 350 mA, ADJ = OPEN

I

LDO

= 1 mA, ADJ = LDO_OUT

I

LDO

= 350 mA, ADJ = LDO_OUT

Voltage Accuracy

Line Regulation

Load Regulation

Dropout Voltage

Current Limit

1

2

Min

3.0

3.35

3.8

Typ

Max

5.5

Unit

V

3.31

3.29

2.86

2.84

2.51

2.49

−3

3

20

300

350

500

+3

V

%

mV/V

mV

mA

I

LDO

= 1 mA to 350 mA, −40°C ≤ T

A

≤ +85°C

I

LDO

= 1 mA

I

LDO

= 1 mA to 350 mA

V

DROP

I

LDPK

LDO_OUT = 98% of LDO_OUT(NOM), I

LDO

= 350 mA

Sets LDO_OUT(NOM) to 2.5 V.

VIN = VIN_1 = VIN_2.

3

Sets LDO_OUT(NOM) to 2.85 V.

4

Sets LDO_OUT(NOM) to 3.3 V.

Rev. 0 | Page 4 of 28

ADD8754

V

COM

AMPLIFIER SPECIFICATIONS

VIN_1 = VIN_2 = SHDN = 5 V, VDD_2 = 14 V, POS = 4.0 V, NEG = OUT, T

A

= 25°C, unless otherwise noted.

Table 3.

Parameter

INPUT CHARACTERISTICS

Offset Voltage

Noninverting Input Bias Current

Input Voltage Range

Common-Mode Rejection Ratio

OUTPUT CHARACTERISTICS

Output Voltage Swing

Output Current

1

POWER SUPPLY

Supply Voltage

Power Supply Rejection Ratio

Supply Current

DYNAMIC PERFORMANCE

Slew Rate

2

Gain Bandwidth

1

2

Symbol

V

OS

I

B

Conditions

Min

Typ

19

50

Max

Unit

mV

nA

V

dB

V

mV

mA

300

VDD_2 − 3

2

CMRR

V

OH

V

OL

I

OUT

VDD_2

PSRR

I

SY

SR

GBW

8

65

V

CM

= 2 V to (VDD_2 − 3) V

I

OUT

(source) = 50 mA

I

OUT

(sink) = 50 mA

60

VDD_2 − 0.5

50

±300

18

70

2

105

1.95

7.5 V ≤ VDD_2 ≤ 18.5 V

No load, POS = VDD_2 /2

R

L

= 10 kΩ, C

L

= 10 pF

−3 dB, R

L

= 10 kΩ, C

L

= 10 pF

V

dB

mA

V/μs

MHz

Not short-circuit protected.

Slew rate is the average of the rising and the falling slew rates.

Rev. 0 | Page 5 of 28

ADD8754

ADD8754 Overview

Preview

Recommended Resources