CD4014BC 8-Stage Static Shift Register
October 1987
Revised January 1999
CD4014BC
8-Stage Static Shift Register
General Description
The CD4014BC is an 8-stage parallel input/serial output
shift register. A parallel/serial control input enables individ-
ual JAM inputs to each of 8 stages. Q outputs are available
from the sixth, seventh and eighth stages. All outputs have
equal source and sink current capabilities and conform to
standard “B” series output drive.
When the parallel/serial control input is in the logical “0”
state, data is serially shifted into the register synchronously
with the positive transition of the clock. When the parallel/
serial control input is in the logical “1” state, data is jammed
into each stage of the register synchronously with the posi-
tive transition of the clock.
All inputs are protected against static discharge with diodes
to V
DD
and V
SS
.
Features
s
Wide supply voltage range:
s
High noise immunity:
3.0V to 15V
0.45 V
DD
(typ.)
s
Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s
5V–10V–15V parametric ratings
s
Symmetrical output characteristics
s
Maximum input leakage:
1
µA
at 15V over full temperature range
Ordering Code:
Order Number
CD4014BCM
CD4014BCN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “x” to the ordering code.
Connection Diagram
Pin Assignments for DIP
Truth Table
CL
Serial
(Note 1) Input
Parallel/
Serial
PI 1
Control
1
1
1
1
0
0
X
0
1
0
1
X
X
X
Q1
(Internal)
0
1
0
1
0
1
Q1
PI n
0
0
1
1
X
X
X
Q
n
0
0
1
1
Q
n−1
Q
n−1
Q
n
X
X
X
X
0
1
X
X
=
Don't care case
No Change
Note 1:
Level change
Top View
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CD4014BC
Absolute Maximum Ratings
(Note 2)
(Note 3)
Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260°C
(Note 3)
700 mW
500 mW
−0.5V
to
+18V
−0.5
to V
DD
+
0.5V
−65°C
to
+150°C
Recommended Operating
Conditions
(Note 3)
Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
3.0V to 15V
0 to V
DD
−40°C
to
+85°C
Note 2:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Note 3:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
Symbol
I
DD
Parameter
Quiescent Device
Current
V
OL
LOW Level
Output Voltage
V
OH
HIGH Level
Output Voltage
V
IL
LOW Level
Input Voltage
V
IH
HIGH Level
Input Voltage
I
OL
LOW Level Output
Current (Note 4)
I
OH
HIGH Level Output
Current (Note 4)
I
IN
Input Current
Conditions
−40°C
Min
Max
20
40
80
0.05
0.05
0.05
4.95
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.52
1.3
3.6
−0.52
−1.3
−3.6
−0.3
0.3
3.5
7.0
11.0
0.44
1.1
3.0
−0.44
−1.1
−3.0
Min
+25°C
Typ
0.1
0.2
0.3
0
0
0
5
10
15
2
4
6
3
6
9
0.88
2.2
8
−0.88
−2.2
−8
−10
−5
10
−5
−0.3
0.3
1.5
3.0
4.0
3.5
7.0
Max
20
40
80
0.05
0.05
0.05
+85°C
Min
Max
150
300
600
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
Units
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
V
DD
=
5V, V
IN
=
V
DD
or V
SS
V
DD
=
10V, V
IN
=
V
DD
or V
SS
V
DD
=
15V, V
IN
=
V
DD
or V
SS
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
4.6V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
|I
O
|
<
1
µA
9.95
14.95
|I
O
|
<
1
µA
11.0
0.36
0.9
2.4
−0.36
−0.90
−2.4
−1.0
1.0
µA
µA
Note 4:
I
OL
and I
OH
are tested one output at a time.
3
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CD4014BC
AC Electrical Characteristics
T
A
=
25
°
C, input t
r
, t
f
=
20 ns, C
L
=
50 pF, R
L
=
200 kΩ
Symbol
t
PHL
, t
PLH
Parameter
Propagation Delay Time
(Note 5)
Conditions
Min
Typ
200
80
60
100
50
40
2.8
6
8
4
12
16
90
40
25
180
80
50
15
15
15
60
40
30
80
40
30
100
50
40
120
80
60
160
80
60
200
100
80
0
10
15
5
110
7.5
Max
320
160
120
200
100
80
Units
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
THL
, t
TLH
Transition Time
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
f
CL
Maximum Clock
Input Frequency
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
15V
Any Input
t
W
Minimum Clock
Pulse Width
t
rCL
, t
fCL
Clock Rise and
Fall Time (Note 6)
t
S
Minimum Set-Up Time
(Note 7) Serial Input
t
H
≥
200 ns
Parallel Inputs
t
H
≥
200 ns
Parallel/Serial Control
t
H
≥
200 ns
t
H
Minimum Hold Time
Parallel/Serial Control
Serial In, Parallel In, t
S
≥
400 ns V
DD
=
10V
C
I
C
PD
Average Input Capacitance
(Note 8)
Power Dissipation Capacitance
(Note 8)
Note 5:
AC Parameters are guaranteed by DC correlated testing.
Note 6:
If more than one unit is cascaded t
rCL
should be made less than or equal to the fixed propagation delay of the output of the driving stage for the esti-
mated capacitive load.
Note 7:
Setup times are measured with reference to clock and a fixed hold time (t
H
) as specified.
Note 8:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note
AN-90.
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