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5962R9665601VXC

Description
4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, FP-16
Categorylogic    logic   
File Size77KB,9 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric Compare View All

5962R9665601VXC Overview

4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, FP-16

5962R9665601VXC Parametric

Parameter NameAttribute value
Parts packaging codeDFP
package instructionDFP, FL16,.3
Contacts16
Reach Compliance Codecompli
Other featuresHOLD MODE; DUAL OUTPUT ENABLE; RADIATION HARDENED
series4000/14000/40000
JESD-30 codeR-CDFP-F16
JESD-609 codee4
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
MaximumI(ol)0.00064 A
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL16,.3
Package shapeRECTANGULAR
Package formFLATPACK
power supply5/15 V
Prop。Delay @ Nom-Su810 ns
propagation delay (tpd)810 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height2.92 mm
Maximum supply voltage (Vsup)18 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose100k Rad(Si) V
Trigger typePOSITIVE EDGE
width6.73 mm
minfmax2.22 MHz
Base Number Matches1
CD4076BMS
December 1992
CMOS 4 -Bit D-Type Registers
Pinout
CD4076BMS
TOP VIEW
M
N
Q1
Q2
Q3
Q4
CLOCK
VSS
1
2
3
4
5
6
7
8
16 VDD
15 RESET
14 DATA 1
13 DATA 2
12 DATA 3
11 DATA 4
10 G2
9 G1
DATA
INPUT
DISABLE
Features
• High Voltage Type (20V Rating)
• Three State Outputs
• Input Disabled Without Gating the Clock
• Gated Output Control Lines for Enabling or Disabling
the Outputs
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
OUTPUT
DISABLE
Functional Diagram
DATA INPUT
DISABLE
G1
9
14
D1
13
D2
12
4D - TYPE
FLIP-FLOPS
WITH
AND-OR
LOGIC
4
Q2
5
10
G2
CLOCK
7
1
OUTPUT
DISABLE
M
2
3
Q1
N
Description
CD4076BMS types are four-bit registers consisting of D-type
flip-flops that feature three-state outputs. Data Disable inputs
are provided to control the entry of data into the flip-flops.
When both Data Disable inputs are low, data at the D inputs
are loaded into their respective flip-flops on the next positive
transition of the clock input. Output Disable inputs are also
provided. When the Output Disable inputs are both low, the
normal logic states of the four outputs are available to the
load. The outputs are disabled independently of the clock by
a high logic level at either Output Disable input, and present
a high impedance.
The CD4076BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H6W
D3
Q3
11
D4
15
RESET
6
Q4
VSS = 8
VDD = 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3325
7-1029

5962R9665601VXC Related Products

5962R9665601VXC 5962R9665601VEC CD4076BFMSR 5962R9665601V9A
Description 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, FP-16 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, FRIT SEALED, CERAMIC, DIP-16 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, UUC16, DIE-16
Parts packaging code DFP DIP DIP DIE
package instruction DFP, FL16,.3 DIP, DIP16,.3 FRIT SEALED, CERAMIC, DIP-16 DIE, DIE OR CHIP
Contacts 16 16 16 16
Reach Compliance Code compli compli not_compliant compliant
series 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000
JESD-30 code R-CDFP-F16 R-CDIP-T16 R-GDIP-T16 R-XUUC-N16
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
Number of digits 4 4 4 4
Number of functions 1 1 1 1
Number of terminals 16 16 16 16
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C -55 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE TRUE
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED UNSPECIFIED
encapsulated code DFP DIP DIP DIE
Encapsulate equivalent code FL16,.3 DIP16,.3 DIP16,.3 DIE OR CHIP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLATPACK IN-LINE IN-LINE UNCASED CHIP
power supply 5/15 V 5/15 V 5/15 V 5/15 V
propagation delay (tpd) 810 ns 810 ns 810 ns 810 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Filter level MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
Maximum supply voltage (Vsup) 18 V 18 V 18 V 18 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V 3 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V
surface mount YES NO NO YES
technology CMOS CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY MILITARY
Terminal form FLAT THROUGH-HOLE THROUGH-HOLE NO LEAD
Terminal location DUAL DUAL DUAL UPPER
total dose 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
minfmax 2.22 MHz 2.22 MHz 8 MHz 8 MHz
Base Number Matches 1 1 1 1
JESD-609 code e4 e4 e0 -
MaximumI(ol) 0.00064 A 0.00064 A 0.00036 A -
Maximum seat height 2.92 mm 5.08 mm 5.08 mm -
Terminal surface GOLD GOLD Tin/Lead (Sn/Pb) -
Terminal pitch 1.27 mm 2.54 mm 2.54 mm -
width 6.73 mm 7.62 mm 7.62 mm -
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