Rev. 1.0, Nov 2010
K8S2815ET(B)E
128Mb E-die NOR FLASH
44FBGA, 7.7x6.2, 0.5mm ball pitch
8M x16, Muxed Burst, Multi Bank
datasheet
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-1-
K8S2815ET(B)E
datasheet
NOR FLASH MEMORY
History
Draft Date
13. May, 2010
28. Oct, 2010
23. Nov, 2010
Remark
Target
Preliminary
Final
Editor
-
-
-
Rev. 1.0
Revision History
Revision No.
0.0
0.5
1.0
- Initial Draft
- Preliminary datasheet.
- Specification is finalized.
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K8S2815ET(B)E
128Mb E-die NOR FLASH 1
datasheet
NOR FLASH MEMORY
Rev. 1.0
1.0 FEATURES................................................................................................................................................................. 4
2.0 GENERAL DESCRIPTION ......................................................................................................................................... 4
3.0 PIN DESCRIPTION .................................................................................................................................................... 5
4.0 44Ball FBGA TOP VIEW (BALL DOWN) .................................................................................................................... 6
5.0 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................. 7
6.0 ORDERING INFORMATION ...................................................................................................................................... 8
7.0 PRODUCT INTRODUCTION...................................................................................................................................... 10
8.0 COMMAND DEFINITIONS ......................................................................................................................................... 11
8.1 COMMAND DEFINITIONS...................................................................................................................................... 11
9.0 DEVICE OPERATION ................................................................................................................................................ 13
9.1 Read Mode .............................................................................................................................................................. 13
9.2 Asynchronous Read Mode ...................................................................................................................................... 13
9.3 Synchronous (Burst) Read Mode ............................................................................................................................ 13
9.4 Output Driver Setting ............................................................................................................................................... 14
9.5 Programmable Wait State ....................................................................................................................................... 14
9.6 Set Burst Mode Configuration Register ................................................................................................................... 14
9.6.1 Extended Configuration Register (option : K8S2615ET(B)E only) .................................................................... 15
9.7 Programmable Wait State Configuration ................................................................................................................. 15
9.8 Burst Read Mode Setting ........................................................................................................................................ 15
9.9 RDY Configuration................................................................................................................................................... 15
9.10 Autoselect Mode.................................................................................................................................................... 16
9.11 Standby Mode ....................................................................................................................................................... 16
9.12 Automatic Sleep Mode .......................................................................................................................................... 16
9.13 Output Disable Mode............................................................................................................................................. 16
9.14 Block Protection & Unprotection ............................................................................................................................ 16
9.15 Hardware Reset..................................................................................................................................................... 17
9.16 Software Reset ...................................................................................................................................................... 17
9.17 Program ................................................................................................................................................................. 17
9.18 Accelerated Program Operation ............................................................................................................................ 17
9.19 Unlock Bypass....................................................................................................................................................... 18
9.20 Chip Erase ............................................................................................................................................................. 18
9.21 Block Erase ........................................................................................................................................................... 18
9.22 Erase Suspend / Resume...................................................................................................................................... 18
9.23 Program Suspend / Resume ................................................................................................................................. 19
9.24 Read While Write Operation .................................................................................................................................. 19
9.25 OTP Block Region ................................................................................................................................................. 19
9.26 Write Pulse “Glitch” Protection .............................................................................................................................. 19
9.27 Low VCC Write Inhibit ........................................................................................................................................... 19
9.28 Logical Inhibit......................................................................................................................................................... 19
9.29 Power-up Protection .............................................................................................................................................. 19
9.30 FLASH MEMORY STATUS FLAGS ...................................................................................................................... 20
10.0 COMMON FLASH MEMORY INTERFACE .............................................................................................................. 22
11.0 ABSOLUTE MAXIMUM RATINGS
..................................................................................................................... 24
12.0 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )
..................................................... 24
13.0 DC CHARACTERISTICS...................................................................................................................................
24
14.0 CAPACITANCE ........................................................................................................................................................ 26
15.0 AC TEST CONDITION
...................................................................................................................................... 26
15.1 Asynchronous Read
........................................................................................................................................29
15.2 Hardware Reset(RESET)
................................................................................................................................32
15.3 Erase/Program Operation................................................................................................................................33
16.0 ERASE/PROGRAM PERFORMANCE
.............................................................................................................. 33
17.0 CROSSING OF FIRST WORD BOUNDARY IN BURST READ MODE ................................................................... 40
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K8S2815ET(B)E
datasheet
NOR FLASH MEMORY
2.0 GENERAL DESCRIPTION
Rev. 1.0
128M Bit (8M x16) Muxed Burst , Multi Bank NOR Flash Memory
1.0 FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 8,386,108 x 16 bit ( Word Mode Only)
•
Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (8Mb Partition)
•
OTP Block : Extra 256-word block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time : 70ns
- Synchronous Random Access Time : 70ns
- Burst Access Time :
14.5ns (54MHz) / 11ns (66MHz) / 9ns (83Mhz) / 7ns (108Mhz)
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with Wrap
•
Block Architecture
- Eight 4Kword blocks and two hundreds fifty-five 32Kword blocks
- Bank 0 contains eight 4 Kword blocks and fifteen 32Kword blocks
- Bank 1 ~ Bank 15 contain two hundred forty 32Kword blocks
•
Reduce program time using the V
PP
•
Support Single & Quad word accelerate program
•
Power Consumption (Typical value, C
L
=30pF)
- Burst Access Current : 24mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 40mA
- Standby Mode/Auto Sleep Mode : 15uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring
RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
- 100K Program / Erase cycles
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Package : Package : 44-ball FBGA Type, 7.7 x 6.2mm
0.5 mm ball pitch
1.0 mm (Max.) Thickness
The K8S2815E featuring single 1.8V power supply is a 128Mbit Synchro-
nous Burst Multi Bank Flash Memory organized as 8Mx16. The memory
architecture of the device is designed to divide its memory arrays into 263
blocks with independent hardware protection. This block architecture pro-
vides highly flexible erase and program capability. The K8S2815E NOR
Flash consists of sixteen banks. This device is capable of reading data from
one bank while programming or erasing in the other bank.
Regarding read access time, the K8S2815E provides an 14.5ns burst
access time and an 70ns initial access time at 54MHz. At 66MHz, the
K8S2815E provides an 11ns burst access time and 70ns initial access time.
At 83MHz, the K8S2815E provides an 9ns burst access time and 70ns ini-
tial access time. At 108MHz, the K8S2815E provides an 7ns burst access
time and 70ns initial access time. The device performs a program operation
in units of 16 bits (Word) and an erase operation in units of a block. Single
or multiple blocks can be erased. The block erase operation is completed
within typically 0.7sec. The device requires 15mA as program/erase current
in the extended temperature ranges.
The K8S2815E NOR Flash Memory is created by using Samsung's
advanced CMOS process technology.
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K8S2815ET(B)E
datasheet
NOR FLASH MEMORY
Pin Function
Address Inputs
Multiplexed Address/Data input/output
Chip Enable
Output Enable
Hardware Reset Pin
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Power Supply
Ground
Rev. 1.0
3.0 PIN DESCRIPTION
Pin Name
A16 - A22
A/DQ0 - A/DQ15
CE
OE
RESET
V
PP
WE
WP
CLK
RDY
AVD
V
CC
V
SS
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