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SIT9120AI-2D2-33E156.250000

Description
LVDS Output Clock Oscillator, 25MHz Min, 212.5MHz Max, 156.25MHz Nom, CMOS,
CategoryPassive components    oscillator   
File Size1MB,13 Pages
ManufacturerSiTime
Environmental Compliance
Download Datasheet Parametric View All

SIT9120AI-2D2-33E156.250000 Overview

LVDS Output Clock Oscillator, 25MHz Min, 212.5MHz Max, 156.25MHz Nom, CMOS,

SIT9120AI-2D2-33E156.250000 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid1424405812
Reach Compliance Codecompliant
Country Of OriginMalaysia, Taiwan, Thailand
YTEOL6.88
Other featuresENABLE/DISABLE FUNCTION; COMPLIMENTARY OUTPUT
maximum descent time0.6 ns
Frequency Adjustment - MechanicalNO
frequency stability25%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Number of terminals6
Nominal operating frequency156.25 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
Output load100 OHM
Package body materialPLASTIC
Encapsulate equivalent codeDILCC6,.2
physical size7mm x 5mm x 0.9mm
power supply3.3 V
Certification statusNot Qualified
longest rise time0.6 ns
Maximum slew rate55 mA
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
SiT9120
Standard Frequency Differential Oscillator
Features
Applications
31 standard frequencies from 25 MHz to 212.5 MHz
LVPECL and LVDS output signaling types
0.6 ps RMS phase jitter (random) over 12 kHz
to 20 MHz bandwidth
Frequency stability as low as ±10 ppm
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2 x 2.5, 5.0 x 3.2 and
7.0 x 5.0 mm x mm
For any other frequencies between 1 to 625 MHz,
refer to
SiT9121
and
SiT9122
datasheet
10GB Ethernet, SONET, SATA, SAS, Fibre Channel,
PCI-Express
Telecom, networking, instrumentation, storage, server
Electrical Characteristics
Table 1. Electrical Characteristics
Parameters
Supply Voltage
Symbol
Vdd
Min.
2.97
2.25
2.25
Output Frequency Range
Frequency Stability
f
F_stab
25
-10
-20
-25
-50
First Year Aging
10-year Aging
Operating Temperature Range
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
F_aging1
F_aging10
T_use
VIH
VIL
Z_in
-2
-5
-40
-20
70%
2
Start-up Time
Resume Time
Duty Cycle
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
T_start
T_resume
DC
Idd
I_OE
I_leak
I_std
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
T_jitt
45
Vdd-1.1
Vdd-1.9
1.2
RMS Phase Jitter (random)
T_phj
Typ.
3.3
2.5
100
6
6
61
1.6
300
1.2
1.2
1.2
0.6
Max.
3.63
2.75
3.63
212.5
+10
+20
+25
+50
+2
+5
+85
+70
30%
250
10
10
55
69
35
1
100
30
Vdd-0.7
Vdd-1.5
2.0
500
115
1.7
1.7
1.7
0.85
Unit
V
V
V
MHz
ppm
ppm
ppm
ppm
ppm
ppm
°C
°C
Vdd
Vdd
ms
ms
%
mA
mA
A
A
mA
V
V
V
ps
ns
ps
ps
ps
ps
25°C
25°C
Industrial
Extended Commercial
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin 1, OE logic high or logic low, or
ST
logic high
Pin 1,
ST
logic low
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time
ST
pin crosses
50% threshold.
Contact SiTime
for tighter duty cycle
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
Termination schemes in
Figures 1 and 2
- XX ordering code
See
list of standard frequencies
Inclusive of initial tolerance, operating temperature,
rated power supply voltage, and load variations
Condition
LVPECL and LVDS, Common Electrical Characteristics
LVPECL, DC and AC Characteristics
ST
= Low, for all Vdds
Maximum average current drawn from OUT+ or OUT-
See
Figure 1(a)
See
Figure 1(a)
See
Figure 1(b)
20% to 80%, see
Figure 1(a)
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds
Rev 1.08
June 25, 2019
www.sitime.com
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