3GPA14-F-80M-240.000 datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 3GPA14-F-80M-240.000

3GPA14-F-80M-240.000: DescriptionLVPECL Output Clock Oscillator, 240MHz Nom, DIP-14/4; CategoryPassive components oscillator; File Size115KB，1 Pages; ManufacturerEuroquartz; Websitehttp://www.euroquartz.co.uk/

Download Datasheet Parametric View All

3GPA14-F-80M-240.000 Overview

LVPECL Output Clock Oscillator, 240MHz Nom, DIP-14/4

3GPA14-F-80M-240.000 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Reach Compliance Code	compli
Maximum control voltage	2 V
Minimum control voltage	1.3 V
maximum descent time	0.7 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	80 ppm
frequency stability	100%
Installation features	THROUGH HOLE MOUNT
Nominal operating frequency	240 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
Output load	50 OHM
physical size	20.2mm x 12.8mm x 5.08mm
longest rise time	0.7 ns
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	NO
maximum symmetry	55/45 %
Base Number Matches	1

Preview

Download Datasheet

View All

EURO

QUARTZ

14 pin Dual-in-Line

Frequency range 60MHz to 240MHz

LVPECL Output

Supply Voltage 3.3 VDC

Phase jitter 0.2ps typical

Pull range from ±30ppm to ±150ppm

DESCRIPTION

GPA14 VCXOs are packaged in a 14 pin dual-in-line package. Typical

phase jitter for GPA series VCXOs is 0.2 ps. Output is LVPECL.

Applications include phase lock loop, SONET/ATM, set-top boxes,

MPEG , audio/video modulation, video game consoles and HDTV.

GPA14 PECL VCXO

60.0MHz to 240.0MHz

OUTLINE & DIMENSIONS

SPECIFICATION

Frequency Range:

Supply Voltage:

Output Logic:

RMS Period Jitter

60.0MHz ~ 120MHz:

120MHz ~ 240MHz:

Peak to Peak Jitter

60.0MHz ~ 120MHz:

120MHz ~ 240MHz:

Phase Jitter:

Initial Frequency Accuracy:

Output Voltage HIGH (1):

Output Voltage LOW (0):

60.0MHz to 240.0MHz

3.3 VDC ±5%

LVPECL

2.5ps typical

4.7ps typical

17.5ps typical

24.5ps typical

0.2ps typical

Tune to the nominal frequency

with Vc= 1.65 ±0.2VDC

Vdd-1.025V minimum

Vdd-0.880V maximum

Vdd-1.810V minimum

Vdd-1.620V maximum

(RL=50 to Vdd-2V)

From ±30ppm to ±150ppm

1.65 ±0.35 Volts

See table

50W into Vdd or Thevenin equiv.

0.5ns typ., 0.7ns max.

20% Vdd to 80% Vdd

50% ±5%

(Measured at Vdd-1.3V)

10ms maximum, 5ms typical

75mA maximum at 212.5MHz

80mA maximum at 622.08MHz

2kV maximum

-55° to +150°C

±2ppm per year maximum

Not implemented - 4 pin package

Fully compliant or non-compliant

PART NUMBERING

Example:

Pulling Range:

Control Voltage Range:

Temperature Stability:

Output Load:

Rise/Fall Times:

Duty Cycle:

Start-up Time:

Current Consumption:

Static Discharge Protection:

Storage Temperature:

Ageing:

Enable/Disable:

RoHS Status:

3GPA14G-B-80N-60.000

Supply Voltage

3 = +3.3V

Series Designator

GPA14

RoHS Status

G = RoHs compliant

Blank = RoHS non-compliant

Stability over temperature range

(See table)

Pullability in ±ppm

Pullability determinator

N = minimum

M = maximum

T = Typical

Frequency in MHz

FREQUENCY STABILITY

Stability Code Stability ±ppm Temp. Range

0°~+70°C

100

0°~+70°C

-40°~+85°C

100

-40°~+85°C

If non-standard frequency stability is required

Use ‘I’ followed by stability, i.e. I20 for ±20ppm

EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE

Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk

Recommended Resources

Counting decoding display circuit

Tremolo generator circuit diagram

Jiali brand electric foot warmer circuit diagram

Sensor OPA604 type low distortion FET input operational amplifier circuit

Using 14-level binary CC4060 to form a quartz second pulse source

Full-bridge converter electrical schematic diagram

RF Basics: RF PCB Design Rules: [i=s]This post was last edited by Jacktang on 2018-3-11 17:33[/i] 1 Silkscreen design in RF PCB design 1.1 Device package silkscreen 1.1.1 The device package silkscreen line must not cross the device ...; Jacktang PCB Design

Why does the output of a sine wave oscillator circuit appear as a square wave?: Can you please help me find out what is wrong? Why is the power output a square wave? I originally wanted a sine wave....; wanghlady Analog electronics

A reward of 1,000 yuan is offered for a code that can light up the keyboard light by writing only a small section in an empty BIOS chip.: A reward of 1,000 yuan is offered for a code that can light up the keyboard light by writing a small section in an empty BIOS chip. If it can perform memory testing and start the graphics card, the re...; aikchun Embedded System

PCB drawing skills: Altium Designer Winter 09 When drawing SCHLIB, how can I change the component pin name to horizontal, or can I only use text for horizontal?How can I change from the left side of the picture to the ri...; chilezhima PCB Design

Urgent help: Is there a device that can directly convert TTL level to 232 and 485 level? It would be best if there is a finished product.: Is there a device that can directly convert TTL level to 232 and 485 level? It would be best if there is a finished product. In other words, this product has three interfaces. It can directly convert ...; anjiu Embedded System

Looking for debugging talents at high prices!: Can debug some domestic online games, find some key information breakpoints! And send them out! Stability! Hiddenness required! If you are interested, add my QQ: 79005380, you can set your own price! ...; sunzhaojie Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components