ICS332-15
Dual Output Clock Synthesizer
Description
The ICS332-15 is a low cost frequency generator that
is factory programmable. Using analog/digital
Phase-Locked Loop (PLL) techniques, the device
accepts a 14.318 MHz crystal or clock input to produce
two output clocks. These clocks can be either 50 MHz,
60 MHz, or 66.6 MHz depending on selection.
The device also has a power down feature that
tri-states the clock outputs and turns off the PLLs when
the PDTS pin is taken low.
Features
•
•
•
•
•
•
•
8-pin SOIC package – Pb-free, RoHS compliant
Zero ppm synthesis error
Input clock or crystal frequency of 14.318 MHz
Two output clocks
Duty cycle of 45/55
3.3 V operating voltage
Advanced, low power CMOS process
Block Diagram
SEL
OTP
ROM
w ith P L L
D iv id e r
V a lu e s
1 4 .3 1 8 M H z C ry s ta l
o r C lo c k
X 1 /IC L K
C ry s ta l
O s c illa to r
X2
P LL
C lo c k
S y n th e s is
and
C o n tro l
C irc u itry
C LK1
C LK2
C a p a cito rs a re re q u ire d
fo r a crysta l in p u t
P D T S (b o th o u tp u ts a n d P L L )
MDS 332-15 F
1
Integrated Device Technology, Inc.
●
Revision 051310
w w w. i d t . c o m
ICS332-15
Dual Output Clock Synthesizer
Pin Assignment
X1/ CLK
VDD
GND
CLK1
1
2
3
4
8
7
6
5
X2
PDTS
SEL
CLK2
Output Clock Selection Table
SEL CLK1 (MHz)
0
1
60
50
CLK2 (MHz)
50
66.6
8 pin (150 mil) SOIC
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
Pin
X1/CLK
VDD
GND
CLK1
CLK2
SEL
PDTS
X2
Pin
XI
Power
Power
Output
Output
Input
Input
XO
Connect to +3.3 V.
Connect to ground.
Pin Description
Connect this pin to a 14.318 MHz clock or crystal input.
CMOS level clock output. Weak internal pull-down when tri-state.
CMOS level clock output. Weak internal pull-down when tri-state.
Select pin for frequency selection on CLK1 and CLK2. Internal pull-up.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up.
Connect this pin to a 14.318 MHz crystal. Float for clock input.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2 = 20].
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS332-15 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
MDS 332-15 F
2
I n t e gra te d D ev i ce Technology, Inc.
Revision 051310
w w w. i d t . c o m
ICS332-15
Dual Output Clock Synthesizer
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS332-15. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS332-15. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.15
Typ.
–
+3.3
Max.
+70
+3.45
Units
°
C
V
MDS 332-15 F
3
I n t e gra te d D ev i ce Technology, Inc.
Revision 051310
w w w. i d t . c o m
ICS332-15
Dual Output Clock Synthesizer
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Supply Current
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage, SEL
Input Low Voltage, SEL
Input High Voltage, ICLK
Input Low Voltage, ICLK
Output High Voltage (CMOS
High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Symbol
VDD
IDD
IDD
PD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
Conditions
No load, PDTS=1
No load, PDTS=0
–
–
Min.
3.15
Typ.
3.3
30
20
Max.
3.45
Units
V
mA
µA
VDD-0.5
–
2
-
–
–
-
-
–
–
–
0.4
-
0.4
–
VDD/2-1
V
V
V
V
V
V
V
V
–
–
I
OH
= -8 mA
I
OH
= -12 mA
I
OL
= 12 mA
VDD/2+1
–
VDD-0.4
2.4
–
–
±70
0.4
V
mA
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature 0 to +70° C
Parameter
Output Rise Time
Output Fall Time
Duty Cycle
Cycle Jitter (short term jitter)
Cycle Jitter (short term jitter)
Input Frequency, clock input
Output Frequency Synthesis
Error
Output Enable Time, PDTS
high to output on
Output Disable Time, PDTS low
to tri-state
Symbol
t
OR
t
OF
t
ja
t
ja
Conditions
0.8 to 2.0 V
2.0 to 0.8 V
Min.
Typ.
0.7
0.6
Max. Units
ns
ns
60
%
ps
ps
MHz
ppm
µs
µs
40
Peak to peak, SEL=0
Peak to peak, SEL=1
±150
±125
14.318
-1
100
2
MDS 332-15 F
4
I n t e gra te d D ev i ce Technology, Inc.
Revision 051310
w w w. i d t . c o m
ICS332-15
Dual Output Clock Synthesizer
Marking Diagram
8
5
332M15LF
######
YYWW
1
4
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “LF” denotes Pb (lead) free package.
4. Bottom marking: (origin)
Origin = country of origin if not USA.
MDS 332-15 F
5
I n t e gra te d D ev i ce Technology, Inc.
Revision 051310
w w w. i d t . c o m
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