EEWORLDEEWORLDEEWORLD

Part Number

Search

ABL2-10.0000MHZ-NY-I-T

Description
Parallel - Fundamental Quartz Crystal, 10MHz Nom, HC/49US, 2 PIN
CategoryPassive components    Crystal/resonator   
File Size2MB,3 Pages
ManufacturerAbracon
Websitehttp://www.abracon.com/index.htm
Environmental Compliance
Download Datasheet Parametric View All

ABL2-10.0000MHZ-NY-I-T Overview

Parallel - Fundamental Quartz Crystal, 10MHz Nom, HC/49US, 2 PIN

ABL2-10.0000MHZ-NY-I-T Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid1481648723
package instructionHC/49US, 2 PIN
Reach Compliance Codecompliant
Country Of OriginMainland China
YTEOL6.25
Other featuresAT-CUT; TR
Ageing5 PPM/YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level100 µW
frequency stability0.003%
frequency tolerance50 ppm
load capacitance18 pF
Installation featuresTHROUGH HOLE MOUNT
Nominal operating frequency10 MHz
Maximum operating temperature85 °C
Minimum operating temperature-30 °C
physical sizeL11.5XB5.0XH2.5 (mm)/L0.453XB0.197XH0.098 (inch)
Series resistance50 Ω
surface mountNO
HC/49US (AT49) MICROPROCESSOR CRYSTAL
ABL2 Series
Moisture Sensitivity Level (MSL) – This product is Hermetically Sealed
and not Moisture Sensitive - MSL = N/A: Not Applicable
Pb
RoHS/RoHS II
11.5 x 5.0 x 2.5 mm
| | | | | | | | | | | | | | |
FEATURES:
• Reduced height at 2.5mm
• High reliability & Low Cost
• Tight stability & extended temperature
• Proven resistance welded metal package
APPLICATIONS:
• Home electronics
• Computers, modems, and communications
• High-precision TCXO and clock applications
• Microprocessors
STANDARD SPECIFICATIONS:
Parameters
Frequency Range
Minimum
3.579545
3.579545
Operation mode
24.01
24.01
Operating Temperature
Storage Temperature
Frequency Tolerance
Frequency Stability over the Operating
Temperature ( ref. to +25°C)
Equivalent series resistance (R1)
Shunt capacitance (C0)
Load capacitance (CL)
Drive Level
Aging @ 25°C per year
Insulation Resistance
Drive Level Dependency (DLD,
Minimum 7 points tested: from 1µW to
500µW)
0
-55
-50
-50
See table 1 below
7
18
100
500
±10
25% of Max
ESR
Max ESR in
Table 1
1000
±5
Typical
Maximum
70
24.0
70.00
50.00
+70
+125
+50
+50
ºC
ºC
ppm
ppm
pF
pF
µW
ppm
MΩ
ppm
MHz
Fundamental AT-
cut (Standard)
3
rd
OT AT-cut
(Standard)
Fundamental AT-
cut or BT-cut (See
options)
See options
See options
See options
Units
Notes
See options
@ 100Vdc ± 15V
Δfrequency (Max –
Min)
ΔESR (Max – Min)
Max ESR over DLD
range
Table 1
Frequency (MHz)
3.579 - 4.999 (Fund.)
5.000 - 5.999 (Fund.)
6.000 - 7.999 (Fund.)
8.000 - 8.999 (Fund.)
9.000 - 9.999 (Fund.)
10.000 - 15.999 (Fund.)
16.000 - 50.000 (Fund.)
24.01 - 31.999 (3rd O/T)
32.000 - 70.00 (3rd O/T)
ABRACON IS
ISO 9001 / QS 9000
ISO 9001:2008
CERTIFIED
ESR(Ω) max.
180
120
100
80
60
50
40
100
80
Revised: 04.21.16
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000
|
fax 949-546-8001
| www.abracon.com
Visit www.abracon.com for Terms & Conditions of Sale

Recommended Resources

Can current DSP realize software radio (SDR) in the absolute sense?
It doesn't necessarily mean high-frequency digital communication, but general medium wave/short wave/FM receivers.What I mean in absolute terms is: antenna->A/D->DSP->power amplifier .Perhaps the bott...
luoshen DSP and ARM Processors
I have a little confusion and hope to get an answer (very anxious)
I am a senior student and will graduate soon. I am studying electronic information engineering. I am now learning 51 single-chip microcomputer because I think it is easy to get started, but I don’t wa...
9043075 Embedded System
[FPGA Open Source Tutorial Series] Chapter 7 State Machine Design Example
[align=center][color=#000][size=15px][b][size=6]State Machine Design Example[/size][/b][/size][/color][/align][align=center][color=#000][size=15px][b][size=6] [/size][/b][/size][/color][/align][align=...
芯航线跑堂 FPGA/CPLD
[Share] Offset Current and Offset Voltage of Op Amp
[table][tr][td]The offset current and offset voltage of the op amp will affect the zero point of the op amp. I have read some information for a few days during the National Day holiday... I will sort ...
linda_xia Analog electronics
PCB Design High-Speed FPGA Design Transceiver Selection Considerations
Currently, many standards and protocols use high-speed transceivers (SERDES) as physical interfaces. The applications of these protocols include communications, computers, industry and storage, as wel...
ESD技术咨询 PCB Design

Popular Articles

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1237  2279  1465  396  630  25  46  30  8  13 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号