EURO
QUARTZ
CMOS SMD 11.4 x 9.6 x 4.7mm, 6 pad
Frequency range 50.01MHz to 200MHz (15pF load)
Frequency range 50.01MHz to 320MHz (10pF load)
LVCMOS Output
Supply Voltage 3.3 VDC
Ultra low jitter less than 1ps
OUTLINE & DIMENSIONS
GF64 VCXO
50.0MHz ~ 320.0MHz
DESCRIPTION
GF64 VCXOs, are packaged in an industry-standard, 6 pad, 11.4mm
x 9.6mm x 4.7mm SMD package. GF64 VCXOs provide excellent
phase jitter performance, less than 1ps.
SPECIFICATION
Frequency Range
Load 15pF:
Load 10pF:
Supply Voltage:
Output Logic:
Integrated Phase Jitter:
Period Jitter RMS:
Period Jitter Peak to peak:
Phase Noise:
Initial Frequency Accuracy:
Output Voltage HIGH (1):
Output Voltage LOW (0):
Pulling Range:
Temperature Stability:
Output Load:
Start-up Time:
Duty Cycle:
Rise/Fall Times:
Current Consumption
<100MHz:
>100MHz:
Linearity:
Modulation Bandwidth:
Input Impedance:
Slope Polarity:
(Transfer function)
50.01MHz to 200.0MHz
50.01MHz to 320.0MHz
3.3 VDC ±5%
LVCMOS
0.4ps typical, 0.5ps maximum
(for 155.250MHz)
3.0ps typical (for 155.250MHz)
20ps typical (for 155.250MHz)
See table below
Tune to the nominal frequency
with Vc= 1.65 ±0.2VDC
90% Vdd minimum
10% Vdd maximum
From ±30ppm to ±150ppm
See table
15pF
10ms maximum, 5ms typical
50% ±5% measured at 50% Vdd
0.7ns typical (15pF load)
30mA maximum (15pF load)
40mA maximum (15pF load)
10% maximum, 6% typical
25kHz minimum
60kW minimum
Monotonic and Positive. (An
increase of control voltage
always increases output
frequency.)
-50° to +100°C
±5ppm per year maximum
Pad 2, Enable high or 70% Vdd
min. applied to Tri-state pad
to enable output.
30% Vdd max. to disable output
(high impedance)
Fully compliant
PHASE NOISE
Offset
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
Frequency 155.25MHz
-62dBc/Hz
-92dBc/Hz
-120dBc/Hz
-132dBc/Hz
-128dBc/Hz
-140dBc/Hz
-150dBc/Hz
Storage Temperature:
Ageing:
Enable/Disable (Tristate):
RoHS Status:
FREQUENCY STABILITY
Stability Code Stability ±ppm Temp. Range
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
PART NUMBER SCHEDULE
Example:
3GF64B-80N-155.25
Supply Voltage
3 = +3.3V
Series Designator
GF64
Stability over
Temperature range (See
table)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
FPGA/CPLD
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