5962-9466307VXX datasheet, PDF

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5962-9466307VXX: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CPGA96, PGA-96; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，177 Pages; ManufacturerCobham Semiconductor Solutions

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5962-9466307VXX Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CPGA96, PGA-96

5962-9466307VXX Parametric

Parameter Name	Attribute value
Parts packaging code	PGA
package instruction	IPGA,
Contacts	96
Reach Compliance Code	unknow
Address bus width	16
boundary scan	YES
maximum clock frequency	24 MHz
letter of agreement	MIL-STD-1553A; MIL-STD-1553B
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	R-CPGA-P96
length	33.274 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	96
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, INTERSTITIAL PITCH
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	3.175 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	26.924 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches	1

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1.0 I

NTRODUCTION

The monolithic SµMMIT provides the system designer with an

intelligent solution to MIL-STD-1553 multiplexed serial data

bus design problems. The SµMMIT is a single-chip device that

implements all three of the defined MIL-STD-1553 functions -

Remote Terminal, Bus Controller, and Monitor. Operating either

autonomously or with a tightly coupled host, the SµMMIT will

solve a wide range of MIL-STD-1553 interface problems. A

powerful RISC processing unit provides automatic message

handling, message status, general status, and interrupt

information. The register-based interface architecture provides

many programmable functions as well as extensive information

pertinent to device maintenance. In either of the three operating

modes, the SµMMIT can access up to 64K x 16 of external

memory (65,536 x 16).

The SµMMIT (which derives its name from serial,

µ−coded,

monolithic, multi-mode, intelligent, terminal) is a powerful

asset to a system designer solving the MIL-STD-1553 problem.

1.1 Remote Terminal Features

The SµMMIT Remote Terminal (SRT) conforms to the

requirements of MIL-STD-1553B, Notice II. In addition to

meeting the requirements of the standard, the SRT has an

extensive list of flexible features to meet any MIL-STD-1553

interface requirement.

1.1.1 Indexing

The SRT can buffer up to 256 receive messages on a subaddress-

by-subaddress basis. Upon reception of the specified number of

messages, the SRT can generate an interrupt by signaling either

the host or subsystem that data is ready for processing. The

indexing feature is commonly used to implement bulk data

transfer algorithms.

1.1.2 Buffer Ping-Pong

To support the transfer of periodic data, double buffering

schemes are often incorporated into remote terminal designs.

Periodic data transfer incorporates the use of two data buffers

per subaddress. The remote terminal processes messages

(receive or transmit) via the designated primary buffer. The host

or subsystem uses the secondary buffer to collect new data for

transmission or processing data received during the defined time

interval. Upon completion of the defined interval, the remote

terminal will switch the primary and secondary data buffers (i.e.,

ping-pong). The SRT supports ping-pong buffering via a user-

selected ping-pong architecture consisting of dual subaddress

data pointers.

1.1.3 Circular Buffers

SµMMIT circular buffer modes simplify the software service

of remote terminals implementing bulk or periodic data

transfers. The SµMMIT architecture allows the user to select

one of two circular buffer modes. The user selects the preferred

mode, at start-up, by writing to Control Register bits.

1.1.4 Internal Illegalization

An internal 256-bit (16 x 16) RAM allows for the illegalization

of all mode codes and subaddresses. The illegalization RAM is

accessed at the beginning of message processing to determine

if the valid command is prohibited. To eliminate host or

subsystem overhead, the SµΜΜIT can initialize the 256-bit

illegalization RAM during the auto-initialization sequence.

1.1.5 Broadcast

Designed to meet the requirements of MIL-STD-1553B Notice

II, the SRT can store all data associated with a broadcast

command in separate memory from non-broadcast commands.

This feature is user-selected via the Descriptor Control word

and internal Control Register.

1.1.6 Interrupt History

A programmable interrupt structure allows the host or

subsystem the flexibility to enter 16 interrupts into a 32-word

buffer before service. This feature allows the logging of multiple

interrupts if immediate service is restricted. The interrupt

structure enters an Interrupt Information Word (IIW) and an

Interrupt Address Word (IAW) indicating what subaddress or

command block generated the interrupt. All modes of operation

support interrupt logging.

1.1.7 Message Information

The SRT generates a Message Information Word and time-tag

(16-bit) for all transacted messages. This information is written

into memory along with message data words. The Message

Information Word contains word count, message errors, and

message type information.

1.2 Bus Controller Features

The SµMMIT Bus Controller (SBC) is a powerful MIL-STD-

1553 bus controller developed to meet the requirements of

multi-frame processing with low host overhead. User-defined

decision making allows the SBC to operate autonomously from

the host until a designated event or series of events has taken

place.

SµMMIT FAMILY - 1

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