U631H16
SoftStore
2K x 8 nvSRAM
Features
F
Packages:
F
High-performance CMOS non-
volatile static RAM 2048 x 8 bits
F
25, 35 and 45 ns Access Times
F
12, 20 and 25 ns Output Enable
Access Times
F
Software STORE Initiation
(STORE Cycle Time < 10 ms)
F
Automatic STORE Timing
F
10 STORE cycles to EEPROM
F
10 years data retention in
EEPROM
F
Automatic RECALL on Power Up
F
Software RECALL Initiation
(RECALL Cycle Time < 20
µs)
F
Unlimited RECALL cycles from
EEPROM
F
Unlimited Read and Write to
SRAM
F
Single 5 V
±
10 % Operation
F
Operating temperature ranges:
5
PDIP28 (300 mil)
PDIP28 (600 mil)
SOP28 (300 mil)
SOP24 (300 mil)
Description
The U631H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U631H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM.
F
F
F
0 to 70 °C
-40 to 85 °C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
Data transfers from the SRAM to
the EEPROM (the STORE opera-
tion), or from the EEPROM to the
SRAM (the RECALL ) operation)
are initiated through software
sequences.
The U631H16 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or write
accesses intervene in the sequence
or the sequence will be aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
n.c.
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
28
27
26
VCC
W
n.c.
A8
A9
n.c.
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
25
4
24
5
23
6
PDIP
22
7
SOP
21
8
28
9
20
10
19
11
18
12
17
13
16
14
15
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
SOP
19
24
18
17
16
15
14
13
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Top View
Top View
1
December 12, 1997
U631H16
Block Diagram
EEPROM Array
32 x (64 x 8)
STORE
Row Decoder
A5
A6
A7
A8
A9
SRAM
Array
32 Rows x
64 x 8 Columns
Store/
Recall
Control
V
CC
V
SS
RECALL
V
CC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Input Buffers
Column I/O
Column Decoder
Software
Detect
A0 - A10
A0 A1 A2 A3 A4 A10
G
E
W
Truth Table for SRAM Operations
Operating Mode
Standby/not selected
Internal Read
Read
Write
*
H
or L
E
H
L
L
L
W
*
H
H
L
G
*
H
L
*
DQ0 - DQ7
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
C-Type
K-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
T
stg
Min.
-0.5
-0.3
-0.3
Max.
7
V
CC
+0.5
V
CC
+0.5
1
Unit
V
V
V
W
°C
°C
°C
0
-40
-65
70
85
150
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
December 12, 1997
U631H16
C-Type
DC Characteristics
Symbol
V
CC
I
OH
I
OL
V
CC
V
OH
V
OL
V
CC
High
Low
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
I
IH
I
IL
V
IH
V
IL
V
CC
V
OH
V
OL
Conditions
Min.
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
V
OH
V
OL
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
= 4.5 V
= 2.4 V
= 0.4 V
= 5.5 V
= 5.5 V
= 0V
= 5.5 V
= 5.5 V
= 0V
1
-1
-1
1
µA
µA
1
-1
-1
1
µA
µA
2.4
0.4
-4
8
8
Max.
Min.
2.4
0.4
-4
Max.
V
V
mA
mA
K-Type
Unit
SRAM MEMORY OPERATIONS
Symbol
Alt.
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
ELQX
t
GLQX
t
AXQX
t
ELICCH
t
EHICCL
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
5
0
3
0
25
Min.
25
25
25
12
13
13
5
0
3
0
35
25
Max.
Min.
35
35
35
20
17
17
5
0
3
0
45
35
Max.
45
Unit
Min.
45
45
45
25
20
20
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No.
1
2
3
4
5
6
7
8
9
Switching Characteristics
Read Cycle
Read Cycle Time
f
Address Access Time to Data Valid
g
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Z
h
G HIGH to Output in High-Z
h
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time after Addr. Change
g
19 Chip Enable to Power Active
e
11 Chip Disable to Power Standby
d, e
e:
f:
g:
h:
Parameter guaranteed but not tested.
Device is continuously selected with E and G both LOW.
Address valid prior to or at the same time with E transition LOW.
Measured
±
200 mV from steady state output voltage.
4
December 12, 1997
U631H16
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
1
t
cR
Ai
Address Valid
2
t
a(A )
DQi
Output
Previous
Data Valid
9
t
v(A)
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
Output Data
Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
1
t
cR
Ai
Address Valid
2
t
a(A )
11
t
PD
5
t
dis(E)
E
7
3
t
a(E)
G
DQi
Output
High Impedance
10
t
PU
t
en(E)
4
t
a(G)
8
t
en(G)
6
t
dis(G)
AAAAAAAAAAA
Output Data
AAAAAAAAAAA
AAAAAAAAAAA
Valid
AAAAAAAAAAA
I
CC
ACTIVE
STANDBY
No. Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Z
h, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2
IEC
25
Min.
Max.
35
Min.
Max.
45
Unit
Min.
Max.
t
AVAV
t
WLWH
t
AVAV
t
cW
t
w(W)
25
20
20
0
20
20
20
12
0
0
10
5
35
30
30
0
30
30
30
18
0
0
13
5
45
35
35
0
35
35
35
20
0
0
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WLEH
t
AVWL
t
AVWH
t
ELWH
t
ELEH
t
DVWH
t
WHDX
t
WHAX
t
WLQZ
t
WHQX
t
DVEH
t
EHDX
t
EHAX
t
AVEL
t
AVEH
t
su(W)
t
su(A)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
en(W)
December 12, 1997
5
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
