HEF4894B
12-stage shift-and-store register LED driver
Rev. 8 — 22 November 2011
Product data sheet
1. General description
The HEF4894B is a 12-stage serial shift register. It has a storage latch associated with
each stage for strobing data from the serial input (D) to the parallel LED driver outputs
(QP0 to QP11). Data is shifted on positive-going clock (CP) transitions. The data in each
shift register stage is transferred to the storage register when the strobe (STR) input is
HIGH. Data in the storage register appears at the output whenever the output enable (OE)
input signal is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4894B
devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed
operation in cascaded systems with a fast clock rise time. The same serial data is
available at QS2 on the next negative going clock edge. This is used for cascading
HEF4894B devices when the clock has a slow rise time.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
and
40 C
to +125
C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +125
C.
Type number
HEF4894BP
HEF4894BT
HEF4894BTT
Package
Name
DIP20
SO20
TSSOP20
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads; body width 7.5 mm
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
Version
SOT146-1
SOT163-1
SOT360-1
NXP Semiconductors
HEF4894B
12-stage shift-and-store register LED driver
4. Functional diagram
3
CP
1
STR
QS1
QS2
QP0
QP1
QP2
2
D
QP3
QP4
QP5
QP6
QP7
QP8
QP9
QP10
QP11
OE
19
7
8
9
18
17
16
15
14
13
11
12
4
5
6
001aai639
Fig 1.
Logic Symbol
2
3
12-STAGE SHIFT REGISTER
12
11
STR
1
12-BIT STORAGE REGISTER
QS2
QS1
D
CP
OE
19
4
QP0
QP1
5
6
QP2
QP3
7
OPEN-DRAIN OUTPUTS
8
QP4
QP5
9
18
QP6
QP7
17
16
QP8
QP9
15
14
QP10
QP11
001aag118
13
Fig 2.
Functional diagram
HEF4894B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 22 November 2011
2 of 19
NXP Semiconductors
HEF4894B
12-stage shift-and-store register LED driver
STAGE 0
D
D
FF0
CP
CP
Q
STAGE 1 TO 10
D
Q10S
STAGE 11
D
Q
FF11
CP
D
Q
QS1
QS2
LATCH
LE
D
Q
D
Q
LATCH
LE
STR
LATCH
LE
OE
QP0 QP1
QP10
QP11
001aag119
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
STR
D
CP
QP0
QP1
QP2
QP3
QP4
QP5
1
2
3
4
5
20 V
DD
19 OE
18 QP6
17 QP7
16 QP8
HEF4894B
6
7
8
9
15 QP9
14 QP10
13 QP11
12 QS2
11 QS1
001aag117
V
SS
10
Fig 4.
Pin configuration
HEF4894B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 22 November 2011
3 of 19
NXP Semiconductors
HEF4894B
12-stage shift-and-store register LED driver
5.2 Pin description
Table 2.
Symbol
D
QP0 to QP11
QS1
QS2
CP
STR
OE
V
DD
V
SS
Pin description
Pin
2
4, 5, 6, 7, 8, 9, 18, 17, 16, 15, 14, 13
11
12
3
1
19
20
10
Description
serial input
parallel output
serial output
serial output
clock input
strobe input
output enable input
supply voltage
ground (0 V)
6. Functional description
Table 3.
Function table
[1]
At the positive clock edge the information in the 10
th
register stage is transferred to the 11
th
register stage and the QS output
Control
CP
[1]
[2]
[3]
Input
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
Parallel output
QP0
Z
Z
no change
Z
L
no change
QPn
Z
Z
no change
QPn 1
QPn1
no change
Serial output
QS1
[2]
Q10S
no change
Q10S
Q10S
Q10S
no change
QS2
[3]
no change
Q11S
no change
no change
no change
Q11S
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition;
Z = high-impedance OFF-state.
Q10S = the data in register stage 10 before the LOW to HIGH clock transition.
Q11S = the data in register stage 11 before the HIGH to LOW clock transition.
HEF4894B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 22 November 2011
4 of 19
NXP Semiconductors
HEF4894B
12-stage shift-and-store register LED driver
clock input
data input
strobe input
output enable
input
internal Q0S
(FF 1)
QP0 output
internal Q10S
(FF 11)
QP10 output
serial QS1
output
serial QS2
output
001aag121
Fig 5.
Timing diagram
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I
I
O
T
stg
T
amb
P
tot
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input leakage current
output current
storage temperature
ambient temperature
total power dissipation
T
amb
=
40 C
to +125
C
DIP20 package
SO20 package
TSSOP20 package
P
[1]
[2]
[3]
[1]
[2]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
QSn outputs; V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
QPn outputs; V
O
< 0.5 V
QSn outputs
QPn outputs
Min
0.5
-
0.5
-
-
-
-
-
65
40
-
-
-
-
Max
+18
10
V
DD
+ 0.5
10
40
10
10
40
+150
+125
750
500
500
100
Unit
V
mA
V
mA
mA
mA
mA
mA
C
C
mW
mW
mW
mW
power dissipation
per output
For DIP20 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO20 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP20 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
HEF4894B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 22 November 2011
5 of 19
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