Document History Page ...................................................... 16
Document Number: 002-00515 Rev. *I
Page 2 of 16
S34MS08G2
1. General Description
The SkyHigh S34MS08G2 8-Gb NAND is offered in 1.8V
CC
with x8 I/O interface. This document contains information for the
S34MS08G2 device, which is a dual-die stack of two S34MS04G2 die. For detailed specifications, please refer to the discrete die
datasheet:
S34MS01G2_04G2.
2. Connection Diagram
Figure 1. 63-BGA Contact, x8 Device, Single CE (Top View)
A1
NC
B1
NC
C3
WP#
D3
VCC
E3
NC
F3
NC
G3
NC
H3
NC
J3
NC
K3
V
SS
L1
NC
M1
NC
L2
NC
M2
NC
C4
ALE
D4
RE#
E4
NC
F4
NC
G4
VCC
H4
I/O0
J4
I/O1
K4
I/O2
C5
VSS
D5
CLE
E5
NC
F5
NC
G5
NC
H5
NC
J5
NC
K5
I/O3
C6
CE#
D6
NC
E6
NC
F6
NC
G6
NC
H6
NC
J6
V
CC
K6
I/O4
C7
WE#
D7
NC
E7
NC
F7
VSS
G7
NC
H7
NC
J7
I/O5
K7
I/O6
C8
RB#
D8
NC
E8
NC
F8
NC
G8
NC
H8
V
cc
J8
I/O7
K8
V
SS
L9
NC
M9
NC
L10
NC
M10
NC
A2
NC
A9
NC
B9
NC
A10
NC
B10
NC
Note
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Document Number: 002-00515 Rev. *I
Page 3 of 16
S34MS08G2
3. Pin Description
Table 1. Pin Description
Pin Name
I/O0 - I/O7
CLE
ALE
CE#
WE#
RE#
WP#
R/B#
VCC
VSS
NC
Description
Inputs/Outputs.
The I/O pins are used for command input, address input, data input, and data output. The
I/O pins float to High-Z when the device is deselected or the outputs are disabled.
Command Latch Enable.
This input activates the latching of the I/O inputs inside the Command Register on
the rising edge of Write Enable (WE#).
Address Latch Enable.
This input activates the latching of the I/O inputs inside the Address Register on the
rising edge of Write Enable (WE#).
Chip Enable.
This input controls the selection of the device. When the device is not busy CE# low selects the
memory.
Write Enable.
This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of
WE#.
Read Enable.
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus.
Data is valid t
REA
after the falling edge of RE# which also increments the internal column address counter by
one.
Write Protect.
The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
Ready Busy.
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
Supply Voltage.
The V
CC
supplies the power for all the operations (Read, Program, Erase). An internal lock
circuit prevents the insertion of Commands when V
CC
is less than V
LKO
.
Ground.
Not Connected.
Notes
2. A 0.1 µF capacitor should be connected between the V
CC
Supply Voltage pin and the V
SS
Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during program and erase operations.
3. An internal voltage detector disables all functions whenever V
CC
is below 1.1V to protect the device from any involuntary program/erase during power transitions.
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