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Datasheet> All Categories > Passive components> capacitor> 8123LCM2535LSN7110
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8123LCM2535LSN7110

Description
CAP,AL2O3,12MF,16VDC,20% -TOL,20% +TOL
CategoryPassive components    capacitor   
File Size659KB，4 Pages
ManufacturerFenghua (HK) Electronics Ltd.
Download Datasheet Parametric View All

8123LCM2535LSN7110 Overview

CAP,AL2O3,12MF,16VDC,20% -TOL,20% +TOL

8123LCM2535LSN7110 Parametric

Parameter NameAttribute value
Objectid1196031810
package instruction,
Reach Compliance Codeunknown
ECCN codeEAR99
YTEOL7
capacitance12000 µF
Capacitor typeALUMINUM ELECTROLYTIC CAPACITOR
diameter25 mm
dielectric materialsALUMINUM
length35 mm
Manufacturer's serial numberLS
negative tolerance20%
Number of terminals2
Maximum operating temperature105 °C
Minimum operating temperature-40 °C
Package formSnap-in
method of packingBulk
polarityPOLARIZED
positive tolerance20%
Rated (DC) voltage (URdc)16 V
ripple current2350 mA
seriesLS
Terminal pitch10 mm

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6701 Compilation Problem
I wrote 6701 today, and the CMD file is as follows: -c -heap 0x1000 -stack 0x1000 MEMORY { VECS: o = 00000000h l = 00000200h BOOTRAM: o = 00000200h l = 00000200h PMEM: o = 00010000h l = 0000FC00h DMEM...
coldsun1982 DSP and ARM Processors
Universal serial port VHDL source program design
Part 1: Serial port receiving program LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; --LIBRARY ALTERA;--USE ALTERA.MAXPLUS2.ALL; LIBRARY LPM;USE...
eeleader FPGA/CPLD
I will be interviewing at Baidu next week. Please give me some advice, education, corrections, help and concern.
[i=s] This post was last edited by astwyg on 2014-5-22 21:29 [/i] I was helping a classmate pass on the news and applied for an internship in Baidu's quality department. Unexpectedly, I received a cal...
astwyg Talking
Help: FPGA and DSP communication problem
FPGA uses DSP's xintf interface to communicate with DSP. I have read a lot of information, but I am still confused. How can I make the timing of FPGA consistent with DSP? I have seen people say that d...
djky183 FPGA/CPLD
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